LEA-6 / NEO-6 / MAX-6 - Hardware Integration Manual
UBX-14054794
Production Information
Hardware description
Page 11 of 85
Name
Component
Function
Comments
U1
LDO
Regulates VBUS (4.4 …5.25 V)
down to a voltage of 3.3 V.
Almost no current requirement (~1 mA) if the GPS receiver is operated as a USB
self-powered device, but if bus-powered LDO (U1) must be able to deliver the
maximum current of ~70 mA. A low-cost DC/DC converter such as LTC3410
from Linear Technology may be used as an alternative.
C23,
C24
Capacitors
Required according to the specification of LDO U1
D2
Protection
diodes
Protect circuit from overvoltage
/ ESD when connecting.
Use low capacitance ESD protection such as ST Microelectronics USBLC6-2.
R4, R5 Serial
termination
resistors
Establish a full-speed driver
impedance of 28…44
A value of 22
is recommended.
R11
Resistor
10 k
is recommended for USB self-powered setup. For bus-powered setup
R11 can be ignored.
Table 1: Summary of USB external components
1.6.3
Display Data Channel (DDC)
An I
2
C compatible Display Data Channel (DDC) interface is available with LEA-6, NEO-6 and MAX-6 modules for
serial communication. For more information about DDC implementation refer to the
u-blox 6 Receiver
Description including Protocol Specification [4].
Background information about the DDC interface is available in
Appendix C.1.
u-blox 6 GPS receivers normally run in I
2
C slave mode. Master Mode is only supported when external
EEPROM is used to store configuration. No other nodes may be connected to the bus. In this case, the
receiver attempts to establish presence of such a non-volatile memory component by writing and reading
from a specific location.
TX ready indicator (data ready) for FW 7.0x. See section
The u-blox 6 DDC interface supports serial communication with u-blox wireless modules. See the
specification of the applicable wireless module to confirm compatibility.
With u-blox 6, when reading the DDC internal register at address 0xFF (messages transmit buffer), the
master must not set the reading address before every byte accessed as this could cause a faulty behavior.
Since after every byte being read from register 0xFF the internal address counter is incremented by one
saturating at 0xFF, subsequent reads can be performed continuously.
Pins SDA2 and SCL2 have internal 13 k
pull-ups. If capacitive bus load is very large, additional external pull-ups
may be needed in order to reduce the pull-up resistance.
Table 2 lists the maximum total pull-up resistor values for the DDC interface. For small loads, e.g. if just
connecting to an external EEPROM, these built-in pull-ups are sufficient.
Load Capacitance
Pull-Up Resistor Value R20, R21
50 pF
N/A
100 pF
18 k
250 pF
4.7 k
Table 2: Pull-up resistor values for DDC interface
