LEA-6 / NEO-6 / MAX-6 - Hardware Integration Manual
UBX-14054794
Production Information
Appendix
Page 80 of 85
The majority of SPI devices provide all four of these lines. Sometimes MOSI and MISO are multiplexed, or else
one is missing. A peripheral device, which must not or cannot be configured, requires no input line but only a
data output. As soon as it gets selected it starts sending data. In some ADCs therefore the MOSI line is missing.
Some devices have no data output (e.g. LCD controllers which can be configured, but cannot send data or status
messages).
The following rules should answer the most common questions concerning these signals:
SCK:
The SCK pin is an output when the SPI is configured as a master and an input when the SPI is
configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal bus
clock. When the master initiates a transfer, eight clock cycles are automatically generated on the SCK pin.
When the SPI is configured as a slave, the SCK pin is an input, and the clock signal from the master
synchronizes the data transfer between the master and slave devices. Slave devices ignore the SCK signal
unless the slave select pin is active low. In both the master and slave SPI devices, data is shifted on one edge
of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by
the SPI transfer protocol.
MISO/MOSI:
The MISO and MOSI data pins are used for transmitting and receiving serial data. When the
SPI is configured as a master, MISO is the master data input line, and MOSI is the master data output line.
When the SPI is configured as a slave, these pins reverse roles.
SCS/SS_N:
In master mode, the SCS output(s) select external slaves (e.g. SCS1_N, SCS2_N). In slave mode,
SS_N is the slave select input. The chip select pin behaves differently on master and slave devices. On a slave
device, this pin is used to enable the SPI slave for a transfer. If the SS_N pin of a slave is inactive (high), the
device ignores SCK clocks and keeps the MISO output pin in the high-impedance state. On a master device,
the SCS pin can serve as a general-purpose output not affecting the SPI.
