LISA-C2 series and FW75-C200 - System Integration Manual
UBX-13000620 - R21
Early Production Information
System description
Page 44 of 103
The I2S interface pins ESD rating is 1 kV (contact discharge). A higher protection level could be required if
the lines are externally accessible on the application board. A higher protection level can be achieved by
mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these
pins.
If the I2S digital audio pins are not used, they can be left unconnected on the application board.
The PCM interface can be used in two modes:
•
Primary PCM running at 2.048 MHz. The primary PCM is disabled at power up or when RESIN_N is asserted.
•
AUX PCM (master) running at 128 kHz
To select the Primary PCM digital audio interface, the AT+USPM command parameters must assume these values
(for more details, refer to u-blox AT Commands Manual [3]):
•
<main_uplink>: “PCM_TX”
•
<main_downlink>: “PCM_RX”
Parameters of digital path can be configured and saved as the normal analog paths, using appropriate path
parameters, as described in the u-blox AT Commands Manual [3] +USGC, +UMGC, +USTN AT commands.
Analog gain parameters of microphone and speakers are unused when digital path is selected.
PCM_TX
and
PCM_RX
are parallel to the analog front end, so resources available for analog path can be
shared:
•
Digital filters and digital gains are available in both uplink and downlink direction. Configure using AT
commands
Refer to the u-blox AT Commands Manual [3]: AT+UI2S command for possible combinations of connection
and settings.
1.11.2.1
Primary PCM mode
Main features of the Primary PCM interface:
Module functions as I2S master (
PCM_CLK
and
PCM_SYNC
signals generated by the module)
PCM_SYNC
signal always runs at 8 kHz
PCM_SYNC
toggles high for 1 or 2 CLK cycles of synchronization (configurable), then toggles low for 16 CLK
cycles of sample width. Frame length can be 1 + 16 = 17 bits or 2 + 16 = 18 bits
PCM_CLK
frequency is fixed at 2.048 MHz
PCM_DOUT
,
PCM_DIN
data are 16 bit words with 8 kHz sampling rate, mono. Data is in 2’s complement
notation. MSB is transmitted first
When
PCM_SYNC
toggles high, the first synchronization bit is always low. Second synchronization bit (present
only in case of 2 bit long
PCM_SYNC
configuration) is MSB of the transmitted word (MSB is transmitted twice in
this case)
PCM_DOUT
changes on
PCM_CLK
rising edge,
PCM_DIN
changes on
PCM_CLK
falling edge
1.11.2.2
AUX PCM mode
The auxiliary codec port operates with standard long-sync timing and a 128 kHz clock. The PCM_SYNC runs at 8
kHz with a 50% duty cycle. Most µ-law and A-law codecs support the 128 kHz AUX_PCM_CLK bit clock.
Module functions as I2S master (
PCM_CLK
and
PCM_SYNC
signals generated by the module)
PCM_SYNC
signal always runs at 8 kHz
PCM_SYNC
toggles high for 1 or 2 CLK cycles of synchronization (configurable), then toggles low for 16 CLK
cycles of sample width. Frame length can be 1 + 16 = 17 bits or 2 + 16 = 18 bits
