TYAN TITAN TURBO ATX-2, Руководство пользователя

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Chapter 4
Fast MA to RAS# delay
Do not change these values unless you change the specifications of the
installed DRAM or the installed CPU.
SDRAM(CAS Lat/RAS-to-CAS)
You can select a combination of CAS latency and RAS-to-CAS delay
in HCLKs of 2/2 or 3/3. The board designer should have set these
values based on the installed DRAM. As above, do not change the
values in this field unless you change the specifications of the installed
DRAM or the installed CPU.
SDRAM Speculative Read
The chipset can guess at a DRAM read address in order to reduce
read latencies. A read request containing the data memory address is
issued by the CPU, and received by the DRAM controller. If this
function is Enabled, the controller issues the read command just before
it has finished decoding the data address.
System BIOS Cacheable
If Enabled, results in better system performance by permitting caching
of the system BIOS ROM at F0000h-FFFFFh. Any program which
tries to write to this memory area may cause a system error.
Video BIOS Cacheable
If Enabled, this function results in better video performance by permit-
ting caching of the video BIOS ROM at C0000h to C7FFFh. Note that
any program which tries to write to this area may cause a system error.
8- and 16-Bit I/O Recovery Time
Because the PCI BUS is so much faster than the ISA BUS, the I/O
recovery mechanism adds BUS clock cycles to the ISA BUS between
PCI-originated I/O cycles. These two fields let you add recovery time
(in BUS clock cycles) for both 8-bit and 16-bit I/O.
Memory Hole at 15M-16M
You can reserve this area of the system memory for ISA adapter
ROM. As long as it is reserved, however, it cannot be cached. Any