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127
TpProcMemBankInterleaveInit
= 0xA139, ///< Bank Interleave Init
TpProcMemNodeInterleaveInit
= 0xA13A, ///< Node Interleave Init
TpProcMemChannelInterleaveInit
= 0xA13B, ///< Channel Interleave Init
TpProcMemEccInitialization
= 0xA13C, ///< ECC initialization
TpProcMemPlatformSpecificInit
= 0xA13D, ///< Platform Specific Init
TpProcMemBeforeAgesaReadSpd
= 0xA13E, ///< Before callout for
"AgesaReadSpd"
TpProcMemAfterAgesaReadSpd
= 0xA13F, ///< After callout for
"AgesaReadSpd"
TpProcMemBeforeAgesaHookBeforeD
ramInit
= 0xA140, ///< Before optional
callout "AgesaHookBeforeDramInit"
TpProcMemAfterAgesaHookBeforeDra
mInit
= 0xA141, ///< After optional callout
"AgesaHookBeforeDramInit"
TpProcMemBeforeAgesaHookBeforeD
QSTraining
= 0xA142, ///< Before optional
callout "AgesaHookBeforeDQSTraining"
TpProcMemAfterAgesaHookBeforeDQ
STraining
= 0xA143, ///< After optional callout
"AgesaHookBeforeDQSTraining"
TpProcMemBeforeAgesaHookBeforeE
xitSelfRef
= 0xA144, ///< Before optional
callout "AgesaHookBeforeDramInit"
TpProcMemAfterAgesaHookBeforeExit
SelfRef
= 0xA145, ///< After optional callout
"AgesaHookBeforeDramInit"
TpProcMemAfterMemDataInit
= 0xA146, ///< After MemDataInit
TpProcMemInitializeMCT
= 0xA147, ///< Before InitializeMCT
TpProcMemLvDdr3
= 0xA148, ///< Before LV DDR3
TpProcMemInitMCT
= 0xA149, ///< Before InitMCT
TpProcMemOtherTiming
= 0xA14A, ///< Before OtherTiming
TpProcMemUMAMemTyping
= 0xA14B, ///< Before UMAMemTyping
TpProcMemSetDqsEccTmgs
= 0xA14C, ///< Before SetDqsEccTmgs
TpProcMemMemClr
= 0xA14D, ///< Before MemClr
TpProcMemOnDimmThermal
= 0xA14E, ///< Before On DIMM
Thermal
TpProcMemDmi
= 0xA14F, ///< Before DMI
TpProcMemEnd
= 0xA150, ///< End of memory code
TpProcS3Init
= 0xA151, ///< Entry point S3Init
TpProcMemSendMRS2
= 0xA180, ///< Sending MRS2
TpProcMemSendMRS3
= 0xA181, ///< Sedding MRS3
TpProcMemSendMRS1
= 0xA182, ///< Sending MRS1
TpProcMemSendMRS0
= 0xA183, ///< Sending MRS0
TpProcMemContinPatternGenRead
= 0xA184, ///< Continuous Pattern
Read
TpProcMemContinPatternGenWrite
= 0xA185, ///< Continuous Pattern Write
TpProcMem2dRdDqsTraining
= 0xA186, ///< Mem: 2d RdDqs Training
begin
TpProcMemBefore2dTrainExtVrefCha
nge
= 0xA187, ///< Mem: Before optional
callout to platform BIOS to change
External Vref during 2d Training
Содержание S8020
Страница 3: ...http www tyan com 3 Glossary 161 Technical Support 167...
Страница 10: ...http www tyan com 10 2 2 Block Diagram S8020 Block Diagram...
Страница 11: ...http www tyan com 11 2 3 Motherboard Mechanical Drawing...
Страница 27: ...http www tyan com 27 3 Connect the heatsink power cable to the mainboard connector...
Страница 34: ...http www tyan com 34 NOTE In the area marked red the PCIe cards or cables must be installed after the memory...
Страница 47: ...http www tyan com 47 3 3 1 1 Node0 Information Only Read...
Страница 55: ...http www tyan com 55...
Страница 56: ...http www tyan com 56 3 3 7 SATA Configuration SATA Mode Select Promontory SATA Type AHCI RAID Auto...
Страница 73: ...http www tyan com 73 3 3 16 AMD CBS...
Страница 78: ...http www tyan com 78 3 3 16 3 UMC Common Options Submenu...
Страница 81: ...http www tyan com 81 3 3 16 4 1 NB Configuration Submenu IOMMU Enable Disable IOMMU Disabled Enabled Auto...
Страница 82: ...http www tyan com 82 3 3 16 5 FCH Common Options Submenu...
Страница 88: ...http www tyan com 88 3 4 1 2 Socket 0 Information...
Страница 92: ...http www tyan com 92 3 5 2 BMC Network Configuration Submenu...
Страница 146: ...http www tyan com 146 Figure 5...
Страница 148: ...http www tyan com 148 Step 5 After setting the capacity move to Create Array and press Enter to begin Figure 7 Figure 7...
Страница 158: ...http www tyan com 158 BIOS Temp Sensor Name Explanation...
Страница 160: ...http www tyan com 160 NOTE...