Tomcat i915 S5120
Chapter 3: BIOS Setup
3-12
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DRAM Timing Selectable
This option permits you to either manually select memory timings, or allow the SPD (Serial
Presence Detect) to determine the said timings automatically.
•
Manual
•
By SPD
Note
On all memory timing settings, lower number is more aggressive.
CAS Latency Time
This setting controls the time delay (in clock cycles - CLKs) that passes before the DRAM
starts to carry out a read command after receiving it. This also determines the number of CLKs
for the completion of the first part of a burst transfer. In other words, the lower the latency, the
faster the transaction.
•
Auto
•
2
•
2.5
•
3
DRAM RAS# to CAS# Delay
This setting is the number of cycles from when a bank activate command is issued until a read
or write command is accepted, that is, before the CAS becomes active.
•
Auto
•
5
•
4
•
3
•
2
DRAM RAS# Precharge
This setting is the number of cycles needed to return data to its original location to close the
bank or number of cycles to page memory before the next bank activate command can be
issued.
•
Auto
•
5
•
4
•
3
•
2
Precharge Delay <tRAS>
This timing controls the length of the delay between the activation and precharge commands --
basically how long after activation can the access cycle be started again. This influences row
activation time that is taken into account when memory has hit the last column in a specific
row, or when an entirely different memory location is requested.
•
Auto
•
4 ~ 10
