Spartan-3E FPGA Industrial Micromodule
User Manual
banks do not need to be disconnected
when power-rails are disabled by the USB
microcontroller.
DIP Switch S4
S4 enables / disables the FPGA configura-
tion through the SPI interface. The FPGA
configuration through the JTAG interface
cannot be disabled.
When S4 is turned on, the FPGA tries to
configure from the SPI Flash memory. The
FPGA can be configured by the JTAG inter-
face at any time.
When S4 is turned off, the FPGA waits to
be configured by the JTAG interface.
For further information about direct (pure
SPI) / indirect (SPI over JTAG) in-system
programming of SPI flash memories,
please see Xilinx Application Notes XAP-
P951 “Configuring Xilinx FPGAs with SPI
Serial Flash” and XAPP974 “Indirect Pro-
gramming of SPI Serial Flash PROMs with
Spartan-3A FPGAs”.
S4
position
SPI (on)*
FPGA configuration: JTAG + SPI
JTAG (off)
FPGA configuration: JTAG
Table 10: S4 (* default: SPI).
Warning!
When downloading via parallel
JTAG programmer to FPGA, it can happen
that programming fails with Error: "
'1' :
Programming terminated. DONE did not
go high.
" Try setting DIP switch S4 to
JTAG-only. A bug in certain Xilinx iMPACT
versions can cause this.
DIP Switches Overview
Figure 11 summarizes functions and loca-
tion of the four DIP switches.
JTAG and SPI
The offset holes for J2 and J3 allow a re-
movable press fit of standard 0.100 inch
header pins to connect the fly wires
without any soldering necessary.
JTAG Header
JTAG signals are available on the dedic-
ated header J2 through a JTAG program-
mer with flying leads as described in Table
11.
Trenz Electronic GmbH
8
Figure 11: DIP switches overview.
