Spartan-3E FPGA Industrial Micromodule
User Manual
Switch S3 back to the “FX PON” position.
In case you uploaded the reference design,
you should see the on-board led blinking
at 0.5 Hz.
For further information about indirect (SPI
over JTAG) in-system programming of SPI
Flash memories, please see Xilinx Applica-
tion Note XAPP974 “Indirect Programming
of SPI Serial Flash PROMs with Spartan-3A
FPGAs”.
Changes from TE0300-00
to TE0300-01
Clocks
TE0300-00 has a 50MHz secondary clock,
whereas TE0300-01 has a 125MHz second-
ary clock.
Volatile Memory Interface
TE0300-00 could access the DDR SDRAM
only
with Xilinx OPB (on-chip peripheral
bus) cores.
TE0300-01 can
also
access the DDR
SDRAM through the dedicated Xilinx MIG
(memory interface generator) memory in-
terface.
B2B Connectors
Contact 14 of connector J5 has been ex-
tended from an input in TE0300-00 to an
I/O in TE0300-01. Therefore hardware
designs developed for the TE0300-00 are
compatible with the TE0300-01 whereas
those developed for the TE0300-01 are
compatible with the TE0300-00 if that con-
tact is configured as input.
Contact 76 of connector J5 has mistakenly
been described as I/O in TE0300-00, but it
has always been an input-only contact as
documented for TE0300-01.
Connector J4 has not been changed.
LED
With TE0300-00, the LED is lit when the
U_LED line on pin T15 is set high whereas
with TE0300-01 the LED is lit when the
U_LED line on pin R10 is set high.
Ordering Information
For the latest product details and available
options, please visit:
www.trenz-electronic.de
shop.trenz-electronic.de
Revision History
Rev
Date
Who
Description
0.1
2008-04-24
FDR
created
1.0
2008-08-01
FDR
completed
1.01 2008-08-08
TT
50MHz to 125MHz
clock
1.02 2008-10-17
FDR
U_LED for
TE0300-00
1.03 2008-10-17
FDR
updated FUT from
1.9 to 2.6
Trenz Electronic GmbH
24