Trenz Electronic TE0300 Скачать руководство пользователя страница 12 | Manualshive

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Trenz Electronic TE0300 Скачать руководство пользователя страница 12

Spartan-3E FPGA Industrial Micromodule

User Manual

TE0300 modules with the following part
numbers

■

TE0300-00

■

TE0300-00-4I5C

■

TE0300-00B

■

TE0300-01

■

TE0300-01B

■

TE0300-01BLP

are assembled with

Qimonda HYB25DC512160CF-6

512Mb DDR SDRAM components. When
developing DDR SDRAM designs with Xilinx
tools, you should select the following
product type:

HYB25D512160BF-6.

SPI Flash

TE0300 modules have a

STMicroelectronics M25P32

32-Mbit, low voltage, serial Flash memory
with 75 MHz SPI bus interface for configur-
ation and operating storage accessible
through USB or SPI.

Serial EEPROM

TE0300 modules have a

Micron Technology 24LC128

128K I2C CMOS Serial EEPROM. It used for
EZ-USB   FX2   firmware,   vendor   ID   and
device   ID   storage.   EEPROM   accessible
through the EZ-USB FX2  microcontroller.

Module Configuration

This section describes how to configure the
TE0300 module and access some of its re-
sources.

The JTAG interface allows a fast, frequent
but volatile configuration of the TE0300
module. However, only through the JTAG

interface it is possible to develop and de-
bug with Xilinx tools (e.g. Xilinx Chip-
Scope, Xilinx Microprocessor Debugger.

The SPI interface allows a fast, frequent
and non-volatile configuration of the
TE0300 module.

Configuration   of   the   TE0300   module
through   a   USB   host   is   recommended   for
occasional,  non-volatile  on-site  operations
such as firmware upgrade.

System Requirements

TE0300 modules can be configured
through a host computer with the following
system requirements:

■

Operating system: Microsoft Windows
2000, Microsoft Windows XP, Microsoft
Vista;

■

Xilinx ISE 10.1 or later for indirect SPI
in-system programming (see Xilinx An-
swer AR #25377);

■

Xilinx EDK for some reference designs;

■

Interface: USB host;

■

JTAG/SPI USB cable with flying leads.

EZ-USB FX2 Microcontroller
Firmware

If the EEPROM has never been pro-
grammed before (virgin board), S1 can be
switched to

EEPROM

. The USB microcon-

troller will detect an empty EEPROM and
will provide its default vendor ID and
device ID to the USB host.

DIP

switch

on (left)

off (right)

S1

EEPROM

-

S2

Run

-

S3

X

X

S4

X

X

Trenz Electronic GmbH

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Содержание TE0300

Страница 1: ...ss mainly focus on the distribution of electronic components Line cards we deal with include Microchip ALPS ROHM Xilinx Pulse ON Everlight and Freescale Main products comprise IC Modules Potentiometer...

Страница 2: ...to board connectors Most I O s on the B2B connectors are routed as LVDS pairs Evenly spread supply pins for good signal integrity Industrial temperature grade avail able on request Low cost versatile...

Страница 3: ...Power Supply 5 FPGA User I Os 6 User Button and LED 7 Configuration Switches 7 JTAG and SPI 8 Clock Networks 9 On board Memories 10 Module Configuration 11 Changes from TE0300 00 to TE0300 01 24 Order...

Страница 4: ...carrier boards It is a powerful system widely used for educational and research activities Boards with other configurations larger FPGA s or equipped with industrial temper ature grade parts are avail...

Страница 5: ...0300 receptacle with its corresponding header The stacking height of the TE0300 B2B connectors is 7 seven mm The stacking height does not include the solder paste thickness USB Connector The micromodu...

Страница 6: ...t used on the baseboard it is re commended to bypass them to ground with 10 nF 100 nF capacitors I O Banks Power Supply The Spartan 3E architecture organizes I Os into four I O banks see Table 3 Bank...

Страница 7: ...from a maximum of 2 inde pendent clock inputs to a maximum of 2 independent digital inputs 21 single ended digital I Os 5 single ended inputs Table 4 summarizes the maximum avail able FPGA user I Os...

Страница 8: ...emory in direct mode For programming the SPI Flash memory in indirect mode over JTAG S2 has to be turned on Run S2 position Run on system running Reset off system reset Table 8 S2 default Run For furt...

Страница 9: ...I Serial Flash and XAPP974 Indirect Pro gramming of SPI Serial Flash PROMs with Spartan 3A FPGAs S4 position SPI on FPGA configuration JTAG SPI JTAG off FPGA configuration JTAG Table 10 S4 default SPI...

Страница 10: ...I programmer with flying leads as described in Table 13 Signal FPGA pin FPGA ball SPI S IO_L01P_2 U3 SPI D IO_L03N_2 T4 SPI Q IO_L16N_2 N10 SPI C IO_L26N_2 U16 Table 12 SPI signal details bank 2 SPI S...

Страница 11: ...3 Digital Clock Manager DCM The DCMs of the FPGA can be used to syn thesize arbitrary clock frequencies from any on board clock network differential clock input pair or single ended clock in put For f...

Страница 12: ...e configuration of the TE0300 module However only through the JTAG interface it is possible to develop and de bug with Xilinx tools e g Xilinx Chip Scope Xilinx Microprocessor Debugger The SPI interfa...

Страница 13: ...ed on the host computer then the easiest way to do it is the following disconnect the micromodule or leave the micromodule unconnected configure the micromodule such that the USB microcontroller will...

Страница 14: ...t S1 is actually switched to EEPROM The USB EEPROM can be programmed by opening the dedicated software Cypress USB Console double click the CyCon sole exe file in the 1st_program CyCon sole folder Cli...

Страница 15: ...wing table DIP switch on left off right S1 EEPROM S2 Run S3 FX2 PON S4 X X Reconnect the USB cable to run the newly uploaded firmware in the USB microcon troller Under the default switch configura tio...

Страница 16: ...300 micromodule can be con figured by means of a firmware upgrade FWU file see next section Micromodule Configuration for further reference The first step in generating the FWU file is to generate the...

Страница 17: ...l Select prepare PROM file Select BIN as output Set PROM File Name to fpga and change Location to a suitable name and location Check Auto Select PROM Navigate to your project s IMPLEMENTA TION folder...

Страница 18: ...ule User Manual The following warning is a normal situ ation This is probably the one and only file with your design Congratulations Click GENERATE FILE or select from menu Operations Generate file Yo...

Страница 19: ...nchanged zip the 3 files change the zip file extension to fwu upload the file as explained in the next section Micromodule Configuration Warning file and path names are given and must NOT be changed M...

Страница 20: ...folder To generate your own firmware upload file please read the document Generating_FWU_file doc in the USB FWUTool folder SPI Direct In System Programming ISP Make sure S2 is switched to Reset off...

Страница 21: ...ce blinking mcs in the TE0300 folder Select the part name corresponding to the SPI flash present on the module STMicro electronics M25P32 a 32 Mbit 4M x 8 Serial Flash memory iMPACT should now look li...

Страница 22: ...t 0 5 Hz For further information about direct pure SPI in system programming of SPI Flash memories please see Xilinx Application Note XAPP951 Configuring Xilinx FPGAs with SPI Serial Flash SPI Indirec...

Страница 23: ...king bit in the TE0300 folder Do not forget to select the Enable Programming of SPI Flash Device Attached to this FPGA option in the same window An Add PROM File dialog window should pop up automatica...

Страница 24: ...Program operation In the Device Programming Properties window just leave the default settings and press the OK button iMPACT will first erase the memory and then write it After successful programming...

Страница 25: ...een ex tended from an input in TE0300 00 to an I O in TE0300 01 Therefore hardware designs developed for the TE0300 00 are compatible with the TE0300 01 whereas those developed for the TE0300 01 are c...

Страница 26: ...does not warrant the accuracy and completeness of the materials in this document Further to the maximum ex tent permitted by applicable law Trenz Electronic disclaims all warranties either express or...

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