Toa EXES-6000, Эксплуатация и устранение неисправностей

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Suppose that the data in Figs. 43 and 44 (1) is
stored at an address of WD.1 (Word 1) of Channel
1 of the CPU memory inside the CP unit.
Fig. 43 System Block Diagram of Data Transmission
and Reception
The 1-word data consisting of 16 bits is transmit-
ted to the DT unit via the 8-bit data bus. Firstly, the
lower 8-bit data (0th bit ~ 7th bit) is transmitted,
and secondly, upper 8-bit data (8th bit ~ 15th bit).
Thirdly, the 5-bit data representing data address
(word number) inside the memory is transmitted.
In the DT unit, each time these data are transmit-
ted, they are latched at the address instructed by
the CPU. The 8-bit address data from the CPU
contains channel number and memory address
(latch IC) inside the DT unit. After the DT unit
receives a complete set of data (
of Fig. 44), the
data is parallel-to-serial converted and phase-
encoded (P.E.). (See
of Fig. 44.) The start and
the end data are added to the beginning and the
end of the P.E. data, respectively so that the DR
unit may know the start and the end of data
reception. (See of Fig. 44.) The P.E. data (pulse)
is transmitted to the DR unit after its high and low
levels are converted into frequencies of 28kHz
and 18kHz, respectively (that is, after being FSK
modulated). See
of Fig. 44.
The DR unit goes through the process reverse to
that of the DT unit, and as a result, it obtains the
same data as that of the CPU memory of the CP
unit. The finally obtained data activates the relays'
contacts of the DR unit, thus permitting controls
of the indicator or controller connected to the DR
unit.
Above explanation is just about the data proces-
sing for (1) word. All the 512-word data are also
always sent out to the DT unit on a word-by-word
basis regardless of the existence of the data in the
words, and are processed in the aforementioned
manner. The data of each of the words 0 through
31 is transmitted from the DT unit to the DR unit
at time intervals of 0.32 seconds.
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