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SLUUBG8B – June 2016 – Revised November 2018

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List of Figures

List of Figures

Jumpers Installation Position

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Bench Setup Diagram and Configuration

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Example Input and Output Waveforms (Channels 3 and 4 are PWM Inputs, Channels 1 and 2 are Outputs)

Overlap is Allowed When DT Connected to VCCI (Channels 3 and 4 are PWM Inputs, Channels 1 and 2
are Driver Outputs)

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Test Waveforms if DT is Left Open (Channel 3 and 4 are PWM Inputs, and Channel 1 and 2 are Driver
Outputs)

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Test Waveforms if DT Connected to R

(Channel 3 and 4 is PWM Inputs, and Channel 1 and 2 is Driver

Outputs)

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UCC21520EVM-286 Schematic

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Top Overlay

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Top Layer

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Bottom Layer

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Bottom Overlay

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List of Tables

Jumpers Setting

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Jumpers Setting

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UCC2x5xxEVM-286 Electrical Specifications

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Two-Channel Function Generator Settings

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Oscilloscope Settings

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UCC2x5xxEVM-286 List of Materials

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Содержание UCC20520EVM286

Страница 1: ...Using the UCC21520EVM 286 UCC20520EVM 286 UCC21521CEVM 286 and UCC21530EVM 286 User s Guide Literature Number SLUUBG8B June 2016 Revised November 2018 ...

Страница 2: ...6 4 Electrical Specifications 6 5 Test Summary 7 5 1 Definitions 7 5 2 Equipment 7 5 3 Equipment Setup 7 6 Power Up and Power Down Procedure 10 6 1 Power Up 10 6 2 Power Down 10 7 Test Waveforms CL 0pF With Different DT Configurations 11 7 1 DT Connected to VCCI J DT Option B in 11 7 2 DT Pin Floating or Left Open J DT Option A in 11 7 3 DT Pin Connected to RDT J DT Option C in 12 8 Schematic 13 9...

Страница 3: ...els 3 and 4 are PWM Inputs Channels 1 and 2 are Driver Outputs 11 5 Test Waveforms if DT is Left Open Channel 3 and 4 are PWM Inputs and Channel 1 and 2 are Driver Outputs 11 6 Test Waveforms if DT Connected to RDT Channel 3 and 4 is PWM Inputs and Channel 1 and 2 is Driver Outputs 12 7 UCC21520EVM 286 Schematic 13 8 Top Overlay 14 9 Top Layer 14 10 Bottom Layer 15 11 Bottom Overlay 15 List of Tab...

Страница 4: ...stest propagation delay of 19 ns and the tightest channel to channel delay matching of less than 5 ns to enable high switching frequency high power density and efficiency The flexible universal capability of the UCC2x5xx with up to 18 V VCCI and 25 V VDDA VDDB allows the device to be used as a low side high side high side low side or half bridge drivers with dual PWM input or single PWM input With...

Страница 5: ...facilitates high voltage isolation test between primary side and secondary side Maximized creepage distance between two output channels Support for half bridge test with MOSFETs IGBTs and SiC MOSFETs with connection to external power stage Testing points allows probing all the key pins of the UCC21520DW UCC20520DW UCC21521CDW UCC21530DWK and other wide body ISO driver family parts 3 2 I O Descript...

Страница 6: ... installed the devices under test are enabled when left open on enable disable pin Option C for UCC21520EVM 286 and UCC20520EVM 286 Option B for UCC21521CEVM 286 and UCC21530EVM 286 Option B Jumper on J DIS 2 and J DIS 1 or J DIS EN 2 and J DIS EN 1 Option C Jumper on J DIS 2 and J DIS 3 or J DIS EN 2 and J DIS EN 3 J DT Option A Jumper not installed interlock with 8 ns dead time Option B Option B...

Страница 7: ...For example V TP12 means the voltage at TP12 V Jxx Voltage at jack terminal Jxx Jxx yy Terminal or pin yy of jack xx DMM Digital multi meters UUT Unit under test EVM Evaluation module assembly in this case the UUT assembly drawings have location for jumpers test points and individual components 5 2 Equipment 5 2 1 Power Supplies Three DC power supply with voltage current above 25 V 1 A for example...

Страница 8: ...l A Pulse DC 5 MHz 50 0 ns 3 3 V 0 V High Z Channel B 100 ns 5 3 4 Oscilloscope Setting Table 5 Oscilloscope Settings BANDWIDTH COUPLING TERMINATION SCALE SETTINGS INVERTING Channel A 500 MHz or above DC 1 MΩ or automatic 10 or automatic OFF Channel B 5 3 5 Jumper Shunt Settings There are two jumpers shunts need to be installed before test 1 Install shunt 1 for header J DIS on pin 2 3 for the UCC2...

Страница 9: ...tor channel A channel applied on JINA TP14 as seen in Figure 2 Function generator channel B channel applied on JINB TP15 as seen in Figure 2 For the UCC20520EVM JINB J INB and TP15 are not installed because the UCC20520 is a single PWM input dual channel output Iso Driver Power supply 1 positive node applied on J1 pin 1 or TP0 and negative node applied on J1 pin 2 or TP13 Power supply 2 positive n...

Страница 10: ... ranges from 1 mA to approximately 3 mA if everything is set correctly 4 Enable the function generator two channel outputs channel A and channel B 5 There will be 1 Stable pulse output on the channel A and channel B in the oscilloscope refer to Figure 3 2 Scope frequency measurement is the same with function generator output 3 DMM 1 and 2 read measurement results should be around 10 mA 2 mA under ...

Страница 11: ... between the outputs of the two channels is decided by inputs see Figure 4 Overlap between two output channels is allowed Figure 4 shows a waveform with overlapped operations Figure 4 Overlap is Allowed When DT Connected to VCCI Channels 3 and 4 are PWM Inputs Channels 1 and 2 are Driver Outputs 7 2 DT Pin Floating or Left Open J DT Option A in Table 2 The dead time DT between the outputs of the t...

Страница 12: ... 8 V and the DT pin current will be less than 10 µA when RDT 100 kΩ Therefore TI recommends to parallel a ceramic bypass capacitor 2 2 nF or above with RDT to achieve better noise immunity and better dead time matching between two channels especially when the dead time is larger than 300 ns The major consideration is that the current through the RDT is used to set the dead time and this current de...

Страница 13: ... TP12 TP17 2 2 RB i Ch A ClassName Ch A i Ch B ClassName Ch B GNDA GNDB INA 1 INB 2 VCCI 3 GND 4 DISABLE 5 DT 6 NC 7 VCCI 8 VSSB 9 OUTB 10 VDDB 11 NC 12 NC 13 VSSA 14 OUTA 15 VDDA 16 U1 UCC21520DW VDDB 51 R4 51 R5 1 4 3 DB C3D02060E www ti com Schematic 13 SLUUBG8B June 2016 Revised November 2018 Submit Documentation Feedback Copyright 2016 2018 Texas Instruments Incorporated Using the UCC21520EVM...

Страница 14: ...0EVM 286 UCC20520EVM 286 UCC21521CEVM 286 and UCC21530EVM 286 9 Layout Diagrams The PCB layout information for UCC21520EVM is shown in Figure 8 Figure 9 Figure 10 and Figure 11 The layouts are the same for UCC20520EVM UCC21521CEVM and UCC21530EVM except for the labels that designate the EVM part number with the device under test Figure 8 Top Overlay Figure 9 Top Layer ...

Страница 15: ... June 2016 Revised November 2018 Submit Documentation Feedback Copyright 2016 2018 Texas Instruments Incorporated Using the UCC21520EVM 286 UCC20520EVM 286 UCC21521CEVM 286 and UCC21530EVM 286 Figure 10 Bottom Layer Figure 11 Bottom Overlay ...

Страница 16: ...nylon Std Std 4 J DIS J DT J INA J INB Header 100 mil 3 1 gold TH J INB is not installed in UCC20520EVM Std Std 1 J1 Connection terminal block 2 position 3 81 mm TH Std Std 2 J2 J3 Terminal block receptacle 3 1 3 81 mm R A TH Std Std 15 JINA JINB TP0 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 Test point miniature red TH JINB and TP4 are not installed in UCC20520EVM Std Std 0 R4 R5 Resistor...

Страница 17: ...ision History NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from A Revision November 2016 to B Revision Page Added device type to include the UCC21530EVM 286 Evalustion Module 4 Changes from Original June 2016 to A Revision Page Added device type to include the UCC20520EVM 286 and UCC21521CEVM 286 Evalustion Modules 4 ...

Страница 18: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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