Appendix A
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VDP FIFO Reset
Address
C9h
7
6
5
4
3
2
1
0
Any data
Writing any data to this register resets the FIFO and clears any data present.
VDP Line Number Interrupt
Address
CAh
7
6
5
4
3
2
1
0
Field 1
Field 2
Line number
enable
enable
This register is programmed to trigger an interrupt when the video line number matches this value in bits 5:0. This interrupt must be enabled
at address C1h. The value of 0 or 1 does not generate an interrupt.
Field 1 enable:
0
Disabled (default)
1
Enabled
Field 2 enable:
0
Disabled (default)
1
Enabled
Line number: (default 00h)
VDP Pixel Alignment
Address
CBh-CCh
Address
7
6
5
4
3
2
1
0
CBh
Switch pixel [7:0]
CCh
Reserved
Switch pixel [9:8]
These registers form a 10-bit horizontal pixel position from the falling edge of sync, where the VDP controller initiates the program from one
line standard to the next line standard. For example, the previous line of teletext to the next line of closed caption. This value must be set
so that the switch occurs after the previous transaction has cleared the delay in the VDP, but early enough to allow the new values to be
programmed before the current settings are required.
VDP FIFO Output Control
Address
CDh
Default (00h)
7
6
5
4
3
2
1
0
Reserved
Host access enable
Host access enable:
This register is programmed to allow host port access to the FIFO or allow all VDP data to go out the video port.
0
Output FIFO data to the video output Y[7:0]
1
Allow host port access to the FIFO data (default)
16
TVP5154A VBI Quick Start
SLEA104 – July 2010
Copyright © 2010, Texas Instruments Incorporated
