Appendix A
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VDP FIFO Read Data
Address
B0h
Read only
7
6
5
4
3
2
1
0
FIFO read data [7:0]
FIFO read data [7:0]: This register is provided to access VBI FIFO data through the host port. All forms of teletext data come directly from
the FIFO, while all other forms of VBI data can be programmed to come from registers or from the FIFO. Current status of the FIFO can be
found at address C6h and the number of bytes in the FIFO is located at address C7h. If the host port is to be used to read data from the
FIFO, the FIFO output control register CDh bit 0 must be set to 1.
VDP Configuration RAM Register
Address
C3h-C5h
Address
7
6
5
4
3
2
1
0
C3h
Configuration data
C4h
RAM address [7:0]
C5h
Reserved
RAM
address 8
The configuration RAM data is provided to initialize the VDP with initial constants. The configuration RAM is 512 bytes organized as 32
different configurations of 16 bytes each. The first 12 configurations are defined for the current VBI standards. An additional 2 configurations
can be used as a custom programmed mode for unique standards like Gemstar.
Address C3h is used to read or write to the RAM. The RAM internal address counter is automatically incremented with each transaction.
Addresses C5h and C4h make up a 9-bit address to load the internal address counter with a specific start address. This can be used to
write a subset of the RAM for only those standards of interest. Registers D0h-FBh must all be programmed with FFh, before writing or
reading the configuration RAM. Full field mode (CFh) must be disabled as well.
14
TVP5154A VBI Quick Start
SLEA104 – July 2010
Copyright © 2010, Texas Instruments Incorporated
