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SLWU086C – November 2013 – Revised January 2016

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TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator

Card User's Guide

User's Guide

SLWU086C – November 2013 – Revised January 2016

TSW14J56 JESD204B High-Speed Data Capture and

Pattern Generator Card User's Guide

The TI TSW14J56 evaluation module (EVM) is a next generation pattern generator and data capture card
used to evaluate performances of the new TI JESD204B device family of high-speed analog-to-digital
converters (ADC) and digital-to-analog converters (DAC). For an ADC, by capturing the sampled data over
a JESD204B interface when using a high-quality, low-jitter clock, and a high-quality input frequency, the
TSW14J56 can be used to demonstrate datasheet performance specifications. Using Altera JESD204B IP
cores, the TSW14J56 can be dynamically configurable to support lane speeds from 600 Mbps to 12.5
Gbps, from 1 to 8 lanes, 1 to 16 converters, and 1 to 4 octets per frame with one firmware build. Together
with the accompanying

High-Speed Data Converter Pro Graphic User Interface

(GUI), it is a complete

system that captures and evaluates data samples from ADC EVMs and generates and sends desired test
patterns to DAC EVMs.

Trademarks

Windows is a trademark of Microsoft Corporation.

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Functionality

The TSW14J56EVM has a single industry standard FMC connector that interfaces directly with TI
JESD204B ADC and DAC EVM's. When used with an ADC EVM, high-speed serial data is captured, de-
serialized and formatted by an Altera Arria V GZ FPGA. The data is then stored into an external DDR3
memory bank, enabling the TSW14J56 to store up to 2G 16-bit data samples. To acquire data on a host
PC, the FPGA reads the data from memory and transmits it on a high speed 32 bit parallel interface. An
onboard high-speed USB 3.0 to parallel converter bridges the FPGA interface to the host PC and GUI.

In pattern generator mode, the TSW14J56 generates desired test patterns for DAC EVMs under test.
These patterns are sent from the host PC over the USB interface to the TSW14J56. The FPGA stores the
data received into the board DDR3 memory module. The data from memory is then read by the FPGA and
transmitted to a DAC EVM across the JESD204B interface connector. The board contains a 100-MHz
oscillator used to generate the DDR3 reference clock and a option for a 10-MHz oscillator for general
purpose use.

Figure 1

shows the TI ADS58J63EVM plugged into the TSW14J56EVM.

Содержание TSW14J56

Страница 1: ...ystem that captures and evaluates data samples from ADC EVMs and generates and sends desired test patterns to DAC EVMs Trademarks Windows is a trademark of Microsoft Corporation 1 Functionality The TS...

Страница 2: ...bps 10 routed transceiver channels 32 Gb DDR3 SDRAM split into four independent 512 164 Gb SDRAMs total of 512M samples each Quarter rate DDR3 controllers supporting up to 800 MHz operation 256K 16 bi...

Страница 3: ...Dynamically reconfigurable transceiver data rate Operating range from 0 600 to 12 5 Gbps Figure 2 shows a block diagram of the TSW14J56 EVM Figure 2 TSW14J56 EVM Block Diagram 1 1 ADC EVM Data Captur...

Страница 4: ...hat are stored inside the on board DDR3 memory To acquire data on a host PC the FPGA reads the data from memory and transmits parallel data to the on board high speed parallel to USB converter 1 2 DAC...

Страница 5: ...tion of the jumpers can be found in Table 2 Table 2 Jumper Description of the TSW14J56 Device Component Description Default SJP1 Power enable to general purpose 10 MHz oscillator Y1 1 to 2 SJP19 SJP21...

Страница 6: ...D27 On if VCCDDR_1 5 V is within specification D30 On if VTTDDR_0 75 V is within specification D34 On if VAR power is present D33 On if USB_1 2 V is within specification D28 On after FPGA completes c...

Страница 7: ...The connector pinout description is shown in Table 4 Table 4 FMC Connector Description of the TSW14J56 FMC Signal Name FMC Pin Standard JESD204 Application Mapping Description RX0_P N C6 and C7 Lane 0...

Страница 8: ...ound device clock Used for special FPGA functions such as sampling SYSREF LA01_P N_CC D8 and D9 DEVCLK C M Mezzanine bound device clock Used for low noise conversion clock SYSREF_P N G9 and G10 SYSREF...

Страница 9: ...inputs connected to the USB 3 0 controller With SJP14 18 in teh default postions this allows the FPGA to be programmed by the HSDC Pro software GUI Every time the TSW14J56EVM is powered down the FPGA...

Страница 10: ...ftware Follow all on screen instructions Accept the license agreements After the installer has finished click Next The GUI executable and associated files reside in the following directory C Program F...

Страница 11: ...the Instrument Option tab at the top left of the GUI and selecting Connect to the Board If this still does not correct this issue check the status of the host USB port When the software is installed...

Страница 12: ...ly reside in the directory called C Program Files x86 Texas Instruments High Speed Data Converter Pro 14J56revD Details Firmware To load a firmware after the GUI has established connection click the S...

Страница 13: ...s Guide available on www ti com If the message appears as shown in Figure 8 verify that all jumpers are in the default position and all power status LEDs are illuminated If certain jumpers are not ins...

Страница 14: ...rce in the USB Interface and Drivers section 10 Revision History Changes from A Revision November 2013 to B Revision Page Changed TSW14J56EVM Interfacing with an ADS42JB49EVM image 2 Changed TSW14J56...

Страница 15: ...TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD...

Страница 16: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments TSW14J56EVM...

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