1
1
2
2
3
3
4
4
5
5
6
6
D
D
C
C
B
B
A
A
2
4
TPS6 59 82_ Ty pe C_ PD
6 /15/2 015
HVL 117 D_ Pow er_ De live ry.Sch D oc
She et Title :
S ize:
Mod. Da te:
Fi le:
She et:
of
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Con tact:
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TPS65 98 2EVM
Proje ct Title:
Des ign ed fo r:
Pu bl ic Re lea se
Assemb ly Va rian t:
-0 01
© Tex as Ins trument s
2015
Dra wn By:
Eng in ee r:
Jaco b O ntive ros
Te xas I nstrume nts an d/or its li cen sors do not wa rran t the accur acy or co mpl eten ess of th is sp ecifi cation or an y inform ation con ta in ed the rei n. Te xas I nstrume nts an d/or its li cen sors do not
w arra nt th at th is de sig n wi ll mee t the spe cifica ti ons, wi ll be suita ble fo r yo ur a ppl ica ti on or fit f or an y particu la r purp ose , or will o pe rate in an i mple men tation . Te x as I nstrume nts an d/or its
l ice nso rs do no t warra nt th at th e de sig n is pro du ction worth y. You sho ul d comp le te ly valida te an d t est yo ur d esi gn im ple men tation to confir m the system f uncti ona li ty f or you r app li catio n.
N ot in versi on contro l
SVN Re v:
H VL11 7
Nu mbe r:
R ev:
D
Back t o Bac k N FET Con figu ratio n
GND
GND
GND
GND
GN D
D1
21 ohm
L1
DNP
R4 8
DN P
0
R6 0
DNP
R5 8
DN P
DNP
R6 4
DN P
0
R6 2
DN P
R 57
DN P
0.01
R1
GND
GND
DNP
R5 1
DN P
DNP
R3 5
DN P
DNP
R 53
DN P
DNP
R 59
DN P
DNP
R 61
DN P
DNP
R 63
DN P
DNP
R 65
GND
DN P
R 50
DN P
DNP
R 47
DN P
0
R 46
DNP
R6 8
DN P
DNP
R 67
DN P
0
R6 6
DN P
R 18
DN P
DNP
R 19
DN P
DNP
R 23
DN P
0
R4 1
0
R39
DNP
R3 7
DN P
GND
0
R 3
0
R2
D NP
0
R 5
0
R6
DNP
220pF
C 19
220pF
C15
GND
1µF
C6
10µF
C1
DNP
R5 4
DN P
VB US
0
R 10
DNP
R 22
D NP
0
R 11
DNP
R 30
D NP
G ND
0.01 µF
C7
0 .0 1µF
C 8
0.01 µF
C9
0.0 1µF
C1 0
D1+
1
D1-
2
NC
6
NC
7
NC
9
NC
10
D2+
4
D2-
5
GND
3
GND
8
U3
TPD4E 05U 06 DQA
D1+
1
D1-
2
NC
6
NC
7
NC
9
NC
10
D2+
4
D2-
5
GND
3
GND
8
U4
TPD4 E05 U06 DQA
7,8
1,2,3
5 ,6 ,
Q2
7 ,8
1 ,2,3
5 ,6,
Q1
GND
6
3
1
8
2
7
5
4
S1
6
3
1
8
2
7
5
4
S2
DN P
1
3
5
6
4
2
7
9
10
8
12
11
14
13
16
15
18
17
20
19
J2
1
3
5
6
4
2
7
9
10
8
12
11
14
13
16
15
18
17
20
19
J3
0 .22µF
C3
3 .83 k
R 75
3.83 k
R 76
3.83 k
R 79
TP1
TP2
TP3
J6
TP4
3 .83k
R 20
100k
R24
GND
100k
R2 6
0 .0 1µF
C 53
GND
Tiv a_5V
Ti va _3V3
1 .0 0k
R4 2
1 .0 0k
R4 3
1 .0 0k
R4 4
1 .0 0k
R4 5
1.00 k
R 12
1.00 k
R 13
1.00 k
R 14
1.00 k
R 15
E xt ernal Power
15.0k
R2 8
DN P
R 31
DN P
DNP
R 34
DN P
0
R 38
0
R40
0
R69
0
R71
DNP
R3 6
DN P
DNP
R3 2
DN P
DNP
R1 7
DN P
DNP
R1 6
DN P
3
1
2
Q4
White
1
2
D3
560
R73
3
1
2
Q5
Whi te
1
2
D4
560
R7 4
3
1
2
Q6
Whi te
1
2
D 5
560
R8 6
3
1
2
Q7
Wh ite
1
2
D 6
560
R 87
3
1
2
Q3
White
1
2
D2
560
R 72
3
1
2
Q8
Wh ite
1
2
D7
560
R 89
3
1
2
Q9
White
1
2
D8
560
R90
G ND
White
1
2
D9
3
1
2
Q1 0
560
R9 6
100k
R70
G ND
SP I _SS Z
B 3
SP I _MO SI
B 4
DEB UG_CT L2
D5
UART_ TX
E 2
DEB UG_CT L1
E 4
UART_RX
F2
SW D_ DATA
F4
R_OS C
G2
SW D_ CLK
G4
AUX _P
J 1
AUX _N
J 2
DEB UG2
K 2
DEB UG4
K 3
LSX _R2P
L4
USB _RP _N
K 5
C_US B_T P
K 6
C_USB _B P
K 7
C_S BU1
K 8
RP D_G1
K 9
RP D_G2
K 10
DEB UG1
L2
DEB UG3
L3
LSX _P 2R
K4
USB _RP _P
L5
C_USB _TN
L6
C_US B _BN
L7
C_S BU2
L8
C_CC1
L9
C_CC2
L10
SP I _CLK
A 3
SP I _MI S O
A 4
HV_G ATE 1
B 9
S ENS E P
B 10
S S
H7
HV_G ATE 2
A 9
SE NS EN
A 10
GP IO0
B 2
I2C_S CL2
B 5
I2C_I RQ2Z
B 6
I2C_I RQ1Z
C1
GP IO1
C2
GP IO4_ HPD
C10
I2C_S DA 1
D1
I2C_S CL1
D2
GP IO7
D7
GP IO2
D10
GP IO5_ HPD
E 10
M RE SE T
E 11
I2C_A DDR
F1
RE SE T
F11
GP IO6
G10
GP IO3
G11
GP IO8
H6
NC
L11
I2C_S DA 2
A 5
RE SE T
D6
U2 A
TPS659 82 ABZQZR
GND
A 1
PP _HV
B 7
GND
B 8
P P _5V 0
B 11
V DDIO
B 1
L DO_1V 8D
A 2
P P _5V 0
C11
GND
D8
P P _5V 0
D11
LDO_B MC
E 1
GND
E 5
GND
E 6
GND
E 7
GND
E 8
GND
F5
GND
F6
GND
F7
GND
F8
BUS P OWERZ
F10
LDO_3V 3
G 1
GND
G5
GND
G6
GND
G7
GND
G8
VI N_3V 3
H1
V OUT _3V 3
H2
GND
H4
GND
H5
GND
H8
P P _CAB LE
H10
VB US
H11
VB US
J 10
VB US
J 11
LDO_1V 8A
K 1
VB US
K 11
GND
L1
PP _HV
A 6
PP _HV
A 7
PP _HV
A 8
P P _5V 0
A 11
U2 B
TPS65 982 ABZQZR
0
R5 6
S ys t em _RES E T
10µF
C1 4
1µF
C16
1µF
C17
G ND
1µF
C1 3
S y s tem _3V 3
L DO_3V 3
GND
GND
GND
0 .1 µF
C 12
22µF
C11
S y s tem _5V
G ND
0 .1 µF
C 5
10µF
C4
G ND
HV _S ourc e
1µF
C1 8
PD & A ltern ate Mo de
Con figu ratio n Swi tc h
De ad Ba tte ry & I2C Ad dr ess
Co nfig ura ti on Sw itch (DN P)
CC1 /CC2 & SBU 1/SBU2
ES D Protectio n
USB 2.0 Top /Bo ttom
ESD P rotectio n
30V Ra ted NFET Re comm end ed
I2C Pu ll- Ups f or I 2C 1 & I2 C2
G ND
GND
GND
100k
R4 9
100k
R52
100k
R55
100k
R21
100k
R25
100k
R29
100k
R33
GND
GND
GND
GND
GND
9 .0 9k
R7 7
9 .09 k
R 78
3 .8 3k
R8 0
V OUT _3V 3
UA RT_T X
UART _RX
AUX _P
A UX_ N
S PI _CLK
I2C_I RQ1Z
I 2C_S DA 1
I 2C_SCL 1
I 2C_IRQ2 Z
I 2C_SDA 2
I 2C_SCL2
GP I O7
GPIO0
GPIO1
LS X _P2 R
M RES E T
RE SE T Z
GP I O6
S P I_M OS I
S P I_M IS O
DE B UG_2
SPI_CSZ
US B 2_RP_N
USB 2_RP _P
DE BUG _1
DEBUG_3
DEBUG_4
GP IO 2
GPIO3
GPIO8
GP I O5_HP D
LS X _R2P
GP I O4_HP D
S WD_CLK
S WD_DATA
LDO_3V 3
V OUT _3V 3
L DO _1V 8D
V B US
VBUS
VBUS
VBUS
C_S B U_N
C_US B _B _N
C_US B _B _P
C_CC2
C_S B U_P
C_USB _T_N
C_US B_T _P
C_CC1
LDO _3V 3
LDO _1V 8D
LDO_3V 3
LDO_3V3
I2C_S DA 1
I2C_SDA2
I 2C_S CL1
I2C_SCL2
I2C_I RQ1Z
I2C_IRQ2Z
C_S B U_N
C_USB _B _N
C_US B_B _P
C_CC2
C_SB U_P
C_US B_T _N
C_US B _T_P
C_CC1
C_US B_B _P
C_USB _B _N
C_US B_T _P
C_USB _T _N
C_CC2
C_CC1
C_S BU_N
C_S BU_P
GP IO 7
DE BUG _2
GP I O0
GPIO8
GPIO2
GPIO6
GPIO3
DE B UG_1
C_CC2
C_CC1
C_US B_T _N
C_US B_T _P
C_US B_B _P
C_US B_B _N
C_S BU_N
C_S BU_P
M RES E T
RE SE TZ
HV _GAT E 1
HV_GATE2
S ENS E P
S ENS E N
RP D_G2
RPD_G1
RPD_G1
RPD_G2
B US PO WERZ
S E NSE N
S E NSE P
HV _GA TE 1
HV_GATE2
DE BUG _1
DEBUG_2
DEBUG_3
DEBUG_4
DEB UG_CT L1
DEBUG_CTL2
GP I O0
GPIO1
GPIO2
GPIO3
GPIO6
GPIO7
GPIO8
G PI O4_HP D
GPIO5_HPD
UA RT_RX
UART _TX
LSX _R2P
LSX_P2R
A UX_P
AUX _N
US B 2_RP _P
US B2_RP _N
S WD_DATA
S WD_CLK
SP I _MO SI
SP I _MI S O
SP I _CSZ
S P I_CLK
I2C_S DA 1
I2C_SDA2
I 2C_S CL1
I2C_SCL2
I2C_ IRQ1Z
I2C_IRQ2Z
DEB UG_CT L1
DEBUG_CTL2
B US PO WERZ
G PI O1
DE B UG_3
DEBUG_4
GP IO5 _HPD
GND
S y st em _5V
GND
A 1
T X1+
A 2
T X1-
A 3
V B US
A 4
CC1
A 5
D+
A 6
D-
A 7
S B U1
A 8
V B US
A 9
RX 2-
A 10
RX 2+
A 11
GND
A 12
G ND
B 1
T X2+
B 2
TX 2-
B 3
VB US
B 4
CC2
B 5
D+
B 6
D-
B 7
S B U2
B 8
VB US
B 9
RX 1-
B 10
RX1+
B 11
G ND
B 12
H1
H1
H2
H2
H3
H3
H4
H4
H5
H5
H6
H6
1
1
2
2
H7
H7
H8
H8
3
3
J 1
20-0 00 00 16- 01
CS
1
DO /I O1
2
WP /I O2
3
GND
4
DI /I O0
5
CLK
6
HO LD/I O3
7
VCC
8
U1
W25 Q8 0D VSNIG
LDO _3V 3
3.3k
R4
3 .3k
R 7
3.3k
R 9
S PI _M OS I
SP I _CLK
GND
S PI _M IS O
LDO_3 V3
S P I_CS Z
GND
0 .1 µF
C2
3.3k
R 8
Schematic
6
Schematic
The circuit diagram in
shows the schematic for page 1 of the TPS65982-EVM. Page 1 includes the TPS65982 IC (U2), the USB Type-C
receptacle (J1), the SPI Flash memory IC (U1), the ESD ICs (U3 and U4), the switch banks (S1 and S2), the Tiva LaunchPad receptacles (J2 and
J3), the External FETs for 5-A delivery (Q1 and Q2), the LEDs (D2–D8) and driving FETs (Q3–Q8, Q13–Q15), and necessary passive circuitry for
the TPS65982.
Figure 3. TPS65982-EVM Schematic Page 1
29
SLVUAF8C – June 2015 – Revised November 2015
TPS65982 Evaluation Module
Copyright © 2015, Texas Instruments Incorporated
