OMAP 2420 and the HWI Module
D-6
D.3.2
Level 2 Interrupt Objects and Properties
There are 32 new HWI interrupt objects defined to correspond to level 2
interrupts 0 through 31. These objects are named HWI_L2_INT0 through
HWI_L2_INT31.
The following parameters have been added to HWI interrupt objects to
allow for static configuration of the level 2 interrupt priorities and mirmask:
❏
iMirMask.
This property is valid for both level 1 and 2 interrupts. It
specifies which level 2 interrupts the dispatcher should disable
before calling this HWI function. This property is writable only when
the useDispatcher property is set to true. (This property is similar to
interruptMask0 and interruptMask1, which deal with level 1
interrupts.)
■
The "self" option causes the dispatcher to disable only the
current interrupt and causes the appropriate interruptBitMask0,
interruptBitMask1, and mirmask values to be generated for the
interrupt being configured.
■
The "all" option disables all level 2 interrupts.
■
The "none" option disables no level 2 interrupts.
■
The "bitmask" option causes the mirmask property to be used to
specify which level 2 interrupts to disable.
❏
mirmask.
This property is valid for both level 1 and 2 interrupts. It
defines a bitmask of the level 2 interrupts to be disabled by the
DSP/BIOS HWI dispatcher when executing this HWI function. This
property is writable only when the useDispatcher property is set to
true. (This property is similar to interruptBitMask0 and
interruptBitMask1, which mask level 1 interrupts.)
❏
priority.
Sets the priority from 0 to 31 of a level 2 interrupt. Zero is
the highest priority. The default priority for a level 2 interrupt matches
its interrupt number. Although this field exists for all HWI interrupt
objects, it cannot be configured for level 1 interrupts. You can change
the priority at run-time using the C55_l2SetIntPriority API.
The following Tconf statements configure the level 2 interrupt 0 to have
a priority of 31 (lowest priority) and a mirmask of 0xffffffff (no other level
2 interrupts enabled while servicing this interrupt):