HWI_enter
2-164
HWI_enter is used by HWIs that are user-dispatched, as opposed to
HWIs that are handled by the HWI dispatcher. HWI_enter must not be
issued by HWIs that are handled by the HWI dispatcher.
If the HWI dispatcher is not used by an HWI object, HWI_enter must be
used in the HWI before any DSP/BIOS API calls that could trigger other
DSP/BIOS objects, such as posting a SWI or semaphore. HWI_enter is
used in tandem with HWI_exit to ensure that the DSP/BIOS SWI or TSK
manager is called at the appropriate time. Normally, HWI_enter and
HWI_exit must surround all statements in any DSP/BIOS assembly
language HWIs that call C functions.
The following list shows the mask families available for the HWI_enter
and HWI_exit API syntax. For each family, several masks are defined
where the "X" indicates which registers are saved. (That is, "X" can be
SAVE_BY_CALLER, SAVE_BY_CALLEE, or BIOS_CONTEXT). For
example, the "C55_ACC_SAVE_BY_CALLEE_MASK" is in the
C55_ACC_X_MASK family. See the c55.h55 file for a complete list of
masks and the example later in this section for a clearer understanding.
Typically "SAVE_BY_CALLER" is used for ISRs written in C.
❏
C55_AR_DR_X_MASK
. Mask of registers belonging to ar0-7, t0-3,
sp-ssp
❏
C55_ACC_X_MASK
. Mask of registers belonging to ac0-3
❏
C55_MISC1_X_MASK
. Mask of registers ier0, ifr0, dbier0, ier1, ifr,
dbier1, st0, st1, st2, st3, trn0, bk03, brc0
❏
C55_MISC2_X_MASK
. Mask of registers dp, cdp, mdp, mdp05,
mdp67, pdp, bk47, bkc, bof01, bof23, bof45, bof67, bofc, ivpd, ivph,
trn1
❏
C55_MISC3_X_MASK
. Mask of registers brc1, csr, rsa0_h_addr,
rsa0, rea0_h_addr, rea0, rsa1_h_addr, rsa1, rea1_h_addr, rea1, rptc
❏
IER0DISABLEMASK / IER0RESTOREMASK
. The IER0 and IER1
masks define which interrupts are to be masked while the HWI is
executing and restored a the end of execution. These arguments
mask ier0 bits to turn off (and to restore).
❏
IER1DISABLEMASK / IER1RESTOREMASK
. These arguments
mask ier1 bits to turn off (and to restore).
❏
MIRDISABLEMASK / MIRRESTOREMASK
. These arguments
mask level 2 interrupt bits (0-31) to turn off (and to restore). (OMAP
2320/2420 only)
❏
MIR1DISABLEMASK / MIR1RESTOREMASK
. These arguments
mask level 2 interrupt bits (32-63) to turn off (and to restore). (OMAP
2320 only)