OMAP 2320 and the HWI Module
C-6
The following Tconf statements configure the level 2 interrupt 0 to have
a priority of 63 (lowest priority) and a mirmask of 0xffffffff (no other level
2 interrupts enabled while servicing this interrupt):
// valid priority values: 0-63
bios.HWI_L2_INT0.priority = 63;
// use dispatcher and enable setting iMirMask, mirmask
bios.HWI_L2_INT0.useDispatcher = true;
// "bitmask" enables writing to mirmask and mir1mask
bios.HWI_L2_INT0.iMirMask = "bitmask";
// no other L2 interrupts while servicing HWI_L2_INT0
bios.HWI_L2_INT0.mirmask = 0xffffffff;
// no other L2 interrupts while servicing HWI_L2_INT0
bios.HWI_L2_INT0.mir1mask = 0xffffffff;
C.3.3
HWI_dispatchPlug API
The range of vector IDs allowed is extended from 0-31 to 0-95. The IDs
32-95 correspond to level 2 interrupts 0-63 respectively. The c55.h file
now includes definitions for C55_L2_INT0 through C55_L2_INT63,
which map to vector IDs 32-95.
The HWI_Attrs structure used by HWI_dispatchPlug has been expanded
to include two additional fields: mirmask and mir1mask. Each of these
fields contains a 32-bit mask to specify which of the additional level 2
interrupts to mask during the interrupt. The mirmask field controls L2
interrupts 0-31. The mir1mask field controls L2 interrupts 32-63.
typedef struct HWI_Attrs {
Uns ier0mask; // Level 1 interrupt masks
Uns ier1mask;
Arg arg; // fxn arg (default = 0)
LgUns mirmask; // Level 2 interrupt mask 0-31
LgUns mir1mask; // Level 2 interrupt mask 32-63
} HWI_Attrs;
The default values of mirmask and mir1mask (provided by HWI_ATTRS)
for all interrupts is consistent with the “self” setting.