Texas Instruments TLV1544EVM Скачать руководство пользователя страница 10

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Running Title—Attribute Reference

viii

Figures

2–1

PCB Layout

2-2

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2–2

PCB Layout

2-3

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2–3

PCB Layout

2-4

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2–4

PCB Layout

2-5

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2–5

PCB Layout

2-6

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3–1

EVM Schematic Diagram

3-2

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3–2

Generation of AVdd/2 with Buffer for Channel A1 Input Biasing with JP6 Removed

3-4

. . . .

4–1

Functional Block Diagram

4-2

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4–2

Microprocessor Interface Timing (Normal Sample Mode, INV CLK = High)

4-3

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4–3

Microprocessor Interface Timing (Normal Sample Mode, INV CLK = Low)

4-3

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4–4

DSP Interface Timing (16-Clock Transfer, Normal Sample Mode, INV CLK = High)

4-4

. . . .

4–5

DSP Interface Timing (16-Clock Transfer, Normal Sample Mode, INV CLK = Low)

4-5

. . . .

4–6

Schematic Diagram

4-10

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Tables

1–1

Maximum I/O CLK Frequency

1-3

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2–1

Component List

2-7

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3–1

Test Connector J7

3-5

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4–1

TLV1544 Serial Interface Modes

4-5

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4–2

Terminal Functions

4-6

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Содержание TLV1544EVM

Страница 1: ...TLV1544EVM Evaluation Module for the TLV1544 10 Bit ADC 1998 Mixed Signal Products User s Guide...

Страница 2: ...Printed in U S A 08 98 SLAU014...

Страница 3: ...TLV1544EVM Evaluation Module for the TLV1544 10 Bit ADC User s Guide Printed on Recycled Paper Literature No SLAU014 August 1998...

Страница 4: ...ED INTENDED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS Inclusion of TI products in such applications is understood to...

Страница 5: ...ocument contains the following chapters Chapter 1 Overview Chapter 2 Physical Description Chapter 3 Circuit Description Chapter 4 Operation Information About Cautions and Warnings This book may contai...

Страница 6: ...terature No SLVS062 SN74AHCT1G04 Literature No SCLS319 Application Reports Interfacing the TLV1544 Analog to Digital Converter to the TMS320C50 DSP literature number SLAA025 FCC Warning This equipment...

Страница 7: ...0 70 11 99 European Factory Repair 33 4 93 22 25 40 Europe Customer Training Helpline Fax 49 81 61 80 40 10 Asia Pacific Literature Response Center 852 2 956 7288 Fax 852 2 956 2200 Hong Kong DSP Hotl...

Страница 8: ...vi...

Страница 9: ...Function 3 3 3 2 1 Inputs 3 3 3 2 2 A0 Voltage Variable Analog Input Potentiometer 3 3 3 2 3 A1 External Input With Voltage Follower Buffer 3 3 3 2 4 Unbuffered Analog Inputs 3 4 3 2 5 Power 3 4 3 2...

Страница 10: ...4 2 4 2 Microprocessor Interface Timing Normal Sample Mode INV CLK High 4 3 4 3 Microprocessor Interface Timing Normal Sample Mode INV CLK Low 4 3 4 4 DSP Interface Timing 16 Clock Transfer Normal Sa...

Страница 11: ...bes some of the factors that must be considered in using the module Topic Page 1 1 Purpose 1 2 1 2 EVM Basic Function 1 2 1 3 Power Requirements 1 3 1 4 I O CLK Requirements 1 3 1 5 I O Interface Conn...

Страница 12: ...these are available for external inputs through BNC connectors The internal analog input consists of an operational amplifier with a potentiometer for observing simple dc measurements The reference vo...

Страница 13: ...p channel A1 depending on the application The positive supply can be lowered to 6 volts and the EVM will maintain the 5 V supply 1 4 I O CLK Requirements The I O CLK can go up to 10 MHz for most of th...

Страница 14: ...l arrangement for J5 Either J5 or J6 can easily be used with the corresponding male ribbon cable plug The two rows of plated through holes designated as JPA shorting jumpers allow the on board signals...

Страница 15: ...nd therefore the clocking edge that is used for data input The analog input that is connected to the TLV1544 is determined by soft ware and any input can be selected for testing The four channels are...

Страница 16: ...1 6 Overview...

Страница 17: ...cription Physical Description This chapter describes the physical characteristics and PCB layout of the EVM and lists the components used on the module Topic Page 2 1 PCB Layout 2 2 2 2 Components Lis...

Страница 18: ...2 2 Physical Description 2 1 PCB Layout The EVM is constructed on a 4 layer 3 inch x 5 25 inch 0 062 inch thick PCB using FR 4 material Figures 2 1 through 2 5 show the individual layers Figure 2 1 P...

Страница 19: ...PCB Layout 2 3 Physical Description Figure 2 2 PCB Layout...

Страница 20: ...PCB Layout 2 4 Physical Description Figure 2 3 PCB Layout...

Страница 21: ...PCB Layout 2 5 Physical Description Figure 2 4 PCB Layout...

Страница 22: ...PCB Layout 2 6 Physical Description Figure 2 5 PCB Layout...

Страница 23: ...RJ 8ENF1000 R26 10 kWpotentiometer multi turn SMD Bourns 3224W 1 103D R30 R31 R32 0 W 1206 SMD Bourns CR1206 J OOOE R34 357 kW 1 1206 SMD Panasonic ERJ 8ENF3573 C1 10 mF 16V Panasonic ECST1CX106R C3 C...

Страница 24: ...DW U3 Low dropout adjustable regulator TI TPS7101QD U4 5 V rail to rail op amp TI TLV2432AID U5 Bipolar op amp TI TLE2027ACD U6 Adjustable voltage reference TI TL1431CD U7 Micro inverter TI SN74AHC1G0...

Страница 25: ...ircuit Description Circuit Description This chapter contains the EVM schematic diagram and discusses the various functions on the EVM Topic Page 3 1 Schematic Diagram 3 2 3 2 Circuit Function 3 3 Chap...

Страница 26: ...48 25 29 33 37 41 45 J6 JPA 1 2 3 4 5 6 7 8 9 10 11 13 EOC CSTART I O_CLK EOC DATA_IN DATA_OUT CS INV_CLK FS TP7 DV DD TP26 RP1A RP1E RP2A RP2B RP1C RP1D RP1F UNUSED C9 0 1 F C14 0 1 F C15 0 1 F 10 Vd...

Страница 27: ...t voltage varies with changes in the supply voltage The full scale output of the TLV2432 will be approximately 10 counts below the nominal full scale digital output of all ones if the analog VCC is us...

Страница 28: ...e impedance must be low for proper slew rate of the input signal The source must provide enough current into 50 pF to arrive at final voltage value within the device specified sampling time Also if th...

Страница 29: ...ignator shorting pins 2 and 3 together The jumper can be changed to position 2 toward the TP27 designator pins 1 and 2 shorted together which removes the ground connection such that a positive voltage...

Страница 30: ...scription 3 2 8 Jumper Arrangement The EVM evaluation can begin with the following shorting plug arrangement JP1 connected to AVdd 2 and 3 shorted JP2 connected to ground 2 and 3 shorted JP3 shorted J...

Страница 31: ...s chapter describes the basic operation of the EVM with a host DSP or processor Topic Page 4 1 TLV1544 Overview 4 2 4 2 Microprocessor Serial Interface 4 8 4 3 DSP Interface 4 9 4 4 TLV1544 to TMS3202...

Страница 32: ...the DSP serial port FSX pin INV CLK state allows DSP or SPI and QSPI timing The CSTART is used for delayed sampling Figure 4 1 Functional Block Diagram Analog MUX Self Test Reference Input Data Regist...

Страница 33: ...see Note A Address Sampled Initialize State Machine and Counter Access Conversion Starts on 10th I O CLK 0s A3 D9 Figure 4 3 Microprocessor Interface Timing Normal Sample Mode INV CLK Low NOTE A To mi...

Страница 34: ...signals No attempt should be made to clock in input data until the minimum CS setup time elapses I O CLK DI DO EOC CS see Note A FS 1 2 3 4 5 6 7 8 9 10 Sample MSB MSB LS B D9 D8 D7 D6 D5 D4 D3 D2 D1...

Страница 35: ...the microprocessor mode or the DSP mode of operation Table 4 1 TLV1544 Serial Interface Modes I O Interface Mode I O Microprocessor Action DSP Action CS Initializes counter Samples state of FS CS Res...

Страница 36: ...lling INV CLK GND edges of I O CLK after CS Wh ti i th DSP d th i t d t i t d MSB fi t d CS When operating in the DSP mode the input data is presented MSB first and is shifted in on the first four fal...

Страница 37: ...on the tenth rising edge of I O CLK regardless of the condition of INV CLK Digital signal processor DSP mode When INV CLK VCC I O CLK clocks the four input data bits into the input data register on t...

Страница 38: ...ion is complete and then the result can be read by the host On the tenth clock falling edge the internal logic takes DATA OUT low to ensure that the remaining bit values are zero if the I O CLK transf...

Страница 39: ...hows after FS and the rest of the output data changes on the rising edge of I O CLK and input data is sampled on the first four falling edges of I O CLK after FS falling when INV CLK is high or the fi...

Страница 40: ...V CLK FS REF REF CS A2 A1 VCC A0 EOC I O CLK DATA IN DATA OUT 1 2 3 4 5 6 7 8 15 14 13 12 11 10 9 0 01 F 4 7 F 0 01 F A0 A1 A2 A3 Analog Inputs 0 01 F TLV1544 INT3 CLKX DX DR XF FSR FSX CLKR See Note...

Страница 41: ...ations Grounding Considerations This appendix contains general information on grounding techniques for a printed circuit board using the TLV1544 Topic Page A 1 Printed Circuit Board Grounding Consider...

Страница 42: ...ound do not produce error voltages in any other ground path Analyzing the current flow paths within the analog section gives an indication of which components can be lumped together to a common ground...

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