Texas Instruments TLV1544EVM, Руководство пользователя

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TLV1544 Overview
4-5 Operation
Figure 4–5. DSP Interface Timing (16-Clock Transfer, Normal Sample Mode,
INV CLK = Low)
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓
before responding to control
input signals. No attempt should be made to clock in input data until the minimum CS setup time elapses.
I/O CLK
DI
DO
EOC
CS
(see
Note
A)
FS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
1 2 3 4 5 6 7 8 9 10
ÎÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎ
ÎÎ
Î ÎÎ
Sample
MSB
MSB LSB
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z Hi-Z
A3 A2 A1 A0
Address Sampled
Conversion Starts on 10th I/O
CLK
↓
(6 I/O CLKs)
Access
11 12 13 14 15
16
Hold/Conversion
CS Rise After 16th I/O CLK
↓
Initialize Counter
0s
td(EOC
↑
-CS
↓
)
Initialize State
Machine
7 I/O CLKs
Maximum
4.1.3 TLV1544 Signal State for Microprocessor and DSP
Table 4–1 lists the signal state in the microprocessor mode or the DSP mode
of operation.
Table 4–1. TLV1544 Serial Interface Modes
I/O
Interface Mode
I/O
Microprocessor Action DSP Action
CS
↓
Initializes counter Samples state of FS
CS
↑
Resets state machine and disable I/O Disables I/O
FS Connects to V
CC
Connects to DSP FSX output.
Initializes the state machine at each CLK
↓
after FS
↑
.
Starts a new cycle at each CLK
↑
following the
initialization (initializes the counter).
I/O CLK
Starts sampling of the analog input started
at fourth I/O CLK
↑
.
Conversion started at tenth I/O CLK
↑
.
Starts sampling of the analog input at fourth I/O CLK
↓
.
Starts sampling of the analog input at tenth I/O CLK
↓
.
DATA IN
Samples input data on I/O CLK
↑
(INV CLK
high).
Samples input data on I/O CLK
↓
(INV CLK
low).
Samples input data at I/O CLK
↓
(INV CLK high).
Samples input data at I/O CLK
↑
(INV CLK low).
DATA
OUT Makes MSB available on CS
↓
.
Changes remaining data on I/O CLK
↓
.
Makes MSB available FS
↓
.
Changes remaining data at each following I/O CLK
↑
after FS
↓
.