TLV1544 Overview
4-3
Operation
Figure 4–2. Microprocessor Interface Timing (Normal Sample Mode, INV CLK = High)
td(EOC
↑
-CS
↓
)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓
before responding
to control input signals. No attempt should be made to clock in input data until the minimum CS setup time elapses.
1
2
3
4
5
6
7
8
9
10
I/O CLK
ÎÎÎ
ÎÎÎ
ÎÎÎ
Conversion
Sample
(6 I/O CLKs)
DI
DO
EOC
CS
MSB
MSB
LSB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
Hi-Z
A3
A2
A1
A0
Rise After 10th I/O CLK
↓
(see Note A)
Address Sampled
Initialize State Machine
and Counter
Access
Conversion Starts on 10th I/O CLK
↑
0s
A3
D9
Figure 4–3. Microprocessor Interface Timing (Normal Sample Mode, INV CLK = Low)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓
before responding
to control input signals. No attempt should be made to clock in input data until the minimum CS setup time has
elapsed.
td(EOC
↑
-CS
↓
)
1
2
3
4
5
6
7
8
9
10
I/O CLK
ÎÎÎÎ
ÎÎÎÎ
Conversion
Sample
DI
DO
EOC
CS
MSB
MSB
LSB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
Hi-Z
A2
A1
A0
Rise After 10th I/O CLK
↓
(see Note A)
Address SampledConversion Starts on 10th I/O CLK
↑
Initialize State Machine
and Counter
(5.5 I/O CLKs)
Access
0s
A3
D9
A3
Содержание TLV1544EVM
Страница 1: ...TLV1544EVM Evaluation Module for the TLV1544 10 Bit ADC 1998 Mixed Signal Products User s Guide...
Страница 2: ...Printed in U S A 08 98 SLAU014...
Страница 8: ...vi...
Страница 16: ...1 6 Overview...
Страница 19: ...PCB Layout 2 3 Physical Description Figure 2 2 PCB Layout...
Страница 20: ...PCB Layout 2 4 Physical Description Figure 2 3 PCB Layout...
Страница 21: ...PCB Layout 2 5 Physical Description Figure 2 4 PCB Layout...
Страница 22: ...PCB Layout 2 6 Physical Description Figure 2 5 PCB Layout...