Texas Instruments TLV1544EVM, Руководство пользователя

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TLV1544 Overview
4-7 Operation
Table 4–2. Terminal Functions (Continued)
Terminal
Name
No.
D
No.
DB
I/O Description
I/O CLK 3 18 I Input/output clock. I/O CLK receives the serial I/O clock input in the two modes
and performs the following four functions in each mode:
Microprocessor mode
•
When INVCLK = V
CC
, I/O CLK clocks the four input data bits into the input
data register on the first four rising edges of I/O CLK after CS
↓
with the
multiplexer address available after the fourth rising edges. When INV CLK
= GND, input data bits are clocked in on the first four falling edges instead.
•
On the fourth falling edge of I/O CLK, the analog input voltage on the
selected multiplex input begins charging the capacitor array and continues
to do so until the tenth rising edge of I/O CLK except in the extended
sampling cycle where the duration of CSTART determines when to end the
sampling cycle.
•
Output data bits change on the first ten falling I/O clock edges regardless
of the condition of INV CLK.
•
I/O CLK transfers control of the conversion to the internal state machine on
the tenth rising edge of I/O CLK regardless of the condition of INV CLK.
Digital signal processor (DSP) mode
•
When INV CLK = V
CC
, I/O CLK clocks the four input data bits into the input
data register on the first four falling edges of I/O CLK after FS
↓
with the
multiplexer address available after the fourth falling edges. When INV CLK
= GND, input data bits are clocked in on the first four rising edges instead.
•
On the fourth rising edge of I/O CLK, the analog input voltage on the
selected multiplex input begins charging the capacitor array and continues
to do so until the tenth falling edge of I/O CLK except in the extended
sampling cycle where the duration of CSTART determines when to end the
sampling cycle.
•
Output data MSB shows after FS
↓
and the rest of the output data bits
change on the first ten rising I/O CLK edges regarless of the condition of INV
CLK.
•
I/O CLK transfers control of the conversion to the internal state machine on
the tenth falling edge of I/O CLK regardless of the condition of INV CLK.
REF+ 15 14 I Upper reference voltage (nominally V
CC
). The maximum input voltage range
is determined by the difference between the voltages applied to REF+ and
REF–.
REF– 14 13 I Lower reference voltage (nominally ground)
V
CC
5 20 I Positive supply voltage