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EVM PCB and High-Speed Design Considerations
SERDES operation and 8B/10B Encoding and Decoding for 20-bit and 16-bit plus control bits are
supported allowing use of a lower cost FPGA solution compared to a FPGA with integrated high-speed
transceivers and built-in SERDES functionality. Latency/depth configurable transmit and receive FIFOs
and loss of signal (LOS) detection of
≤
75 mVdfpp are just a few of the other features supported in this
device.
Configuration of the TLK6002 on a per-channel basis is available by way of accessing a register space of
control bits available through a two-wire access port called the Management Data Input/Output (MDIO)
interface as defined in Clause 22 of the IEEE 802.3 Ethernet Specification.
(1)
The TLK6002EVM board can be run from a single, 5-V power supply or 5-Vdc transformer. All voltages
needed are regulated down through onboard LDO regulators which can be adjusted to the appropriate
minimum, nominal, and maximum values through a single jumper location.
Voltage monitor circuits with LEDs are included on all voltage rails for easy debugging and identification of
valid power rails.
All data I/O signals are broken out to connectors for easy and rapid prototyping. All control signals are
easily controlled through shunts on header blocks.
PRBS latch circuits have been added to aid in PRBS BER tests.
The EVM board functionality can be easily expanded through the use of the three peripheral ports. Optical
modules, clock oscillator generators, and FPGAs are just a few possible uses for these ports.
2
EVM PCB and High-Speed Design Considerations
The board can be used to evaluate device parameters in addition to acting as a guide for high-speed
board layout. As the frequency of operation increases, the board designer must take special care to
ensure that the highest signal integrity is maintained. To achieve this, the board's impedance is controlled
to 50
Ω
for both the high-speed differential serial and low-speed parallel data and clock connections. Vias
are minimized and, when necessary, are designed to minimize impedance discontinuities along the
transmission line. Because the board contains both serial and parallel transmission lines, care was taken
also to control trace length mismatch (board skew) to less than ±0.5 mil.
Overall, the board layout is designed and optimized to support high-speed operation. Thus, understanding
impedance control and transmission line effects are crucial when designing high-speed boards. Some of
the advanced features offered by this board include:
•
PCB (printed-circuit board) is designed for optimal high-speed signal integrity.
•
SMP and parallel header fixtures are easily connected to test equipment.
•
All input/output signals are accessible for rapid prototyping.
•
The entire board can be powered from a single, 5-V power supply where the power planes can be
supplied through onboard regulators or through separate banana jacks for isolation.
•
Onboard capacitors provide ac coupling of high-speed transmit and receive signals.
•
External parallel loop-back function can be achieved easily using simple 0.1-inch jumpers.
•
Entire board can operate from a single 5-V power supply or from individual power supplies.
•
Voltage monitoring LED circuits provide quick indication that the voltage is within specification.
(1)
The MDIO register map is located within the TLK6002, Dual-Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver data sheet.
5
SLLU132 – October 2010
TLK6002 Dual-Channel, 0.47-Gbps to 6.25-Gbps, Multi-Rate Transceiver
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