Control and Output Status Signals
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If Channel B ARS is not enabled (Rate B = 000/001/010/011/111):
Channel B SERDES settings are determined by Channel B MDIO registers. CLK_OUT_P/N is
selected by CLK_OUT_SEL. See Table 9 of the TLK6002 data sheet (
SLLSE34
) for additional
details on CLK_OUT_P/N.
Channel A and B must not be in slave mode simultaneously. Both directions of Channel A are
controlled by these input signals.
The RATE_B2 pin must be routed to an uninstalled header so that it can be driven externally
in the event that device debug is required. In application mode, it must be biased with a pullup
or pulldown resistor and not connected directly to a power or ground plane.
CODEB_EN: Encoder/Decoder Channel B Enable: When this pin is asserted high, the internal 8b/10b
encoder/decoder is enabled. This signal is ORed with MDIO register bits, and must be pulled low through
a resistor if software control is desired. This pin must be routed to an uninstalled header so that it can be
driven externally in the event that device debug is required. In application mode, it must be biased with a
pullup or pulldown resistor and not connected directly to a power or ground plane.
LOSB: Channel B Receive Loss Of Signal (LOS) Indicator.
LOSB = 0, signal detected.
LOSB = 1, loss of signal.
Loss of signal detection is based on the input signal level. When RXBP/N has an input signal
of
≤
75 mVdfpp, LOSB is asserted (if enabled). The input signal must be greater than or equal
to 150mVdfpp for this function to operate reliably.
Other functions can be observed on LOSB real time, configured via MDIO.
During device reset (RESET_N asserted low), this pin is driven low. During pin-based power
down (PD_TRXB_N asserted low), this pin is floating. During register-based power down (1.15
asserted high), this pin is floating.
It is highly recommended that LOSB be brought to an easily accessible point on the
application board (header) in the event that debug is required.
PD_TRXB_N: Transceiver Power Down. When this pin is held low (asserted), Channel B is placed in
power-down mode. When de-asserted, Channel B operated normally. After de-assertion, a software data
path reset must be issued through the MDIO interface.
AMUXB: SERDES Channel B Analog Testability I/O. This signal is used during the device manufacturing
process. It must be left unconnected in the device application.
AMUXA: SERDES Channel A Analog Testability I/O. This signal is used during the device manufacturing
process. It must be left unconnected in the device application.
TESTEN: Test Enable. This signal is used during the device manufacturing process. It must be grounded
through a resistor in the device application board. The application board must allow the flexibility of easily
reworking this signal to a high level if device debug is necessary (by including an uninstalled resistor to
VDDO2).
PRBS_EN: Enable PRBS: When this pin is asserted high, the internal PRBS generator and verifier
circuits are enabled on both transmit and receive data paths of both channels. This signal is logically
ORed with an MDIO register bit. PRBS 2
31
-1 is selected by default, and can be changed in MDIO register
7.10:8. Note that PRBS is not possible in eighth rate mode.
The PRBS_EN pin must be routed to an uninstalled header so that it can be driven externally in the event
that device debug is required. In application mode, it must be biased with a pullup or pulldown resistor (or
allow for an isolation mechanism from the onboard driver) and not connected directly to a power or ground
plane.
CLK_OUT_SEL: Output Clock Selection. If ARS is not enabled and CLK_OUT_SEL is low, Channel A
recovered byte clock is output onto CLK_OUT_P/N. If ARS is not enabled and CLK_OUT_SEL is high,
Channel B recovered byte clock is output onto CLK_OUT_P/N. If software control is desired, (registered
bit 0.6), this input signal must be tied low. See Figure 4, “TLK6002 Reference Clock/Output Clock
Architecture” of the TLK6002 data sheet (
SLLSE34
) for more detail. If ARS is enabled, the function of
CLK_OUT_SEL is shown in Table 9 of the TLK6002 data sheet.
14
TLK6002 Dual-Channel, 0.47-Gbps to 6.25-Gbps, Multi-Rate Transceiver
SLLU132 – October 2010
Evaluation Module
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