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Control and Output Status Signals
If Channel B ARS is not enabled (Rate B = 000/001/010/011/111):
Channel A SERDES settings are determined by Channel A MDIO registers. CLK_OUT_P/N is
selected by CLK_OUT_SEL. See Table 9 of the TLK6002 data sheet (
SLLSE34
) for additional
details on CLK_OUT_P/N.
Channel A and B must not be in slave mode simultaneously. Both directions of Channel A are
controlled by these input signals.
The RATE_A[2] pin must be routed to an uninstalled header so that it can be driven externally in
the event that device debug is required. In application mode, it must be biased with a pullup or
pulldown resistor and not connected directly to a power or ground plane.
CODEA_EN: Encoder/Decoder Channel A Enable: When this pin is asserted high, the internal 8b/10b
encoder/decoder is enabled. This signal is ORed with MDIO register bits and must be pulled low through
a resistor if software control is desired. This pin must be routed to an uninstalled header so that it can be
driven externally in the even that device debug is required. In application mode, it must be biased with a
pullup or pulldown resistor and not connected directly to a power or ground plane.
LOSA: Channel A Receive Loss Of Signal (LOS) Indicator.
LOSA = 0, signal detected.
LOSA = 1, loss of signal.
Loss of signal detection is based on the input signal level. When RXAP/N has an input signal
of
≤
75mVdfpp, LOSA is asserted (if enabled). The input signal must be greater than or equal
to 150mVdfpp for this function to operate reliably.
Other functions can be observed on LOSA real time, configured via MDIO.
During device reset (RESET_N asserted low), this pin is driven low. During pin-based power
down (PD_TRXA_N asserted low), this pin is floating. During register-based power down (1.15
asserted high), this pin is floating.
It is highly recommended that LOSA be brought to an easily accessible point on the
application board (header) in the event that debug is required.
PD_TRXA_N: Transceiver Power Down. When this pin is held low (asserted), Channel A is placed in
power-down mode. When de-asserted, Channel A operated normally. After de-assertion, a software data
path reset must be issued through the MDIO interface.
RATE_B[2:0]: Channel B Rate select pins. These pins put channel B into one of the four supported
(full/half/quarter/eighth) channel operation rates, enable software control, or enable Auto Rate Sense
(ARS):
000 – Full Rate mode
001 – Half Rate mode
010 – Quarter Rate mode
011 – Eighth Rate mode
100 – Software Selectable Rate
101 – Channel A Auto Rate Sense (ARS) Function Enabled.
Channel B SERDES settings are determined by Channel B ARS machine. CLK_OUT_P/N is
selected by CLK_OUT_SEL. See Table 9 of the TLK6002 data sheet (
SLLSE34
) for additional
details on CLK_OUT_P/N.
110 – Channel B Auto Rate Sense (ARS) Function Enabled.
Channel B SERDES settings are determined by Channel B ARS machine. CLK_OUT_P/N is
not selected by CLK_OUT_SEL. Channel A may not be simultaneously configured with
RATE_A = 110 with respect to CLK_OUT_P/N; this setting has the highest priority. See Table
9 of the TLK6002 data sheet (
SLLSE34
) for additional details on CLK_OUT_P/N.
111 – Channel B Auto Rate Sense (ARS) Function Enabled – Slave Mode
If Channel B ARS is enabled (Rate B = 101 or 110 only):
Channel B SERDES settings are determined by Channel B ARS machine. CLK_OUT_P/N is
not selected by CLK_OUT_SEL. See Table 9 of the TLK6002 data sheet (
SLLSE34
) for
additional details on CLK_OUT_P/N.
13
SLLU132 – October 2010
TLK6002 Dual-Channel, 0.47-Gbps to 6.25-Gbps, Multi-Rate Transceiver
Evaluation Module
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