GND
GND
MDC
MDIO
MDIO
JMP30
ALL NON-LABELED PINS
ARE NO-CONNECTS
MDIO
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8
MDIO
The TLK6002 supports the Management Data Input/Output (MDIO) Interface as defined in Clause 22 of
the IEEE 802.3 Ethernet Specification. The MDIO allows register-based management and control of the
serial links. Normal operation of the TLK6002 is possible without the use of this interface; however, some
additional features are accessible only through the MDIO interface.
The MDIO Management Interface consists of a bidirectional data path (MDIO) and a clock reference
(MDC). The port address is determined by control pins PRTAD[4:0
In Clause 22, the top four control pins PRTAD[4:1] determine the device port address. In this mode, the
two individual channels in TLK6002 are classified as two different ports. Therefore, any PRTAD[4:1] value
has two ports per TLK6002. The TLK6002 responds if the four MSBs of PHY address field on MDIO
protocol (PA[4:1]) matches PRTAD[4:1]. The LSB of PHY address field (PA[0]) determines which
channel/port within the TLK6002 to respond to.
If PA[0] = 1’b0, TLK6002’s Channel A responds.
If PA[0] = 1’b1, TLK6002’s Channel B responds.
Write transactions which address an invalid register or read-only registers are ignored. Read transactions
of invalid registers return a 0.
The bidirectional MDIO pin must be externally pulled up to 1.5 V or 1.8 V (VDDO) with an appropriate
resistor value as per the IEEE802.3 Clause 22/45 MDIO Standard.
The supplied MDIO EVM uses an FPGA with 2.5-V I/O signal levels whereas the TLK6002 requires either
1.5-V or 1.8-V I/O levels on these signals. Therefore, bidirectional level shifters have been provided on
board that level shift the 2.5-V MDIO and MDC signals to the appropriate 1p5/8V levels. If a different
MDIO controller id used that already has 1.5-V or 1.8-V signal levels, resistors R530, R531, R532, and
R533 can be removed; thus, disconnecting the level shifters and resistors R469 and R470 can be installed
which connects the TLK6002 MDIO and MDC signal pins directly to the pins of JMP30. A third option of
using NFETs as level shifters has also been provided, if this option is desired in the end application.
Removing resistors R530, R531, R532, and R533, as well R469 and R470 if they were installed, and
installing an appropriate NFET such as Fairchild’s FDV301N allows for this third option of level shifting to
be evaluated.
Figure 10. TLK6002 EVM MDIO Connector (JMP30)
18
TLK6002 Dual-Channel, 0.47-Gbps to 6.25-Gbps, Multi-Rate Transceiver
SLLU132 – October 2010
Evaluation Module
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