19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
P
5
/8
V
T
D
A
0
..
1
9
T
D
A
0
..
1
9
R
D
A
0
..
1
9
G
N
D
G
N
D
JMP145
JMP38
JMP37
G
N
D
G
N
D
T
X
C
L
K
A
R
X
C
L
K
A
PARALLEL
LOOPBACK
Parallel Signals
www.ti.com
Figure 14. Parallel Loopback Example
Additional GND and VDD pins have been added into the header block for several reasons. The GND pins
next to the RDA/B and TDA/B pins provide a convenient ground reference for a scope probe or coaxial
cables. The additional TDA/B row and VDD pins allow a static pattern to be driven into the TDA/B bus by
placing jumpers across either the TDA and 1p5/8V pins for a HIGH, or TDA/B and GND pins for a LOW
eliminating the need for cables during quick tests. The extra row of TDA/B can also be used to monitor the
signals on the TDA/B pins.
Figure 15
shows a clock pattern (01010101010101010101) on TDA[19:0].
22
TLK6002 Dual-Channel, 0.47-Gbps to 6.25-Gbps, Multi-Rate Transceiver
SLLU132 – October 2010
Evaluation Module
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