MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
www.ti.com
5.23
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
Figure 5-18
and
Figure 5-19
)
PARAMETER
TEST CONDITIONS
V
CC
MIN
MAX
UNIT
SMCLK, ACLK
f
USCI
USCI input clock frequency
f
SYSTEM
MHz
Duty cycle = 50% ±10%
2.2 V
110
t
SU,MI
SOMI input data setup time
ns
3 V
75
2.2 V
0
t
HD,MI
iSOMI input data hold time
ns
3 V
0
2.2 V
30
t
VALID,MO
SIMO output data valid time
UCLK edge to SIMO valid, C
L
= 20 pF
ns
3 V
20
5.24
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
Figure 5-20
and
Figure 5-21
)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX UNIT
STE lead time
t
STE,LEAD
2.2 V, 3 V
50
ns
STE low to clock
STE lag time
t
STE,LAG
2.2 V, 3 V
10
ns
Last clock to STE high
STE access time
t
STE,ACC
2.2 V, 3 V
50
ns
STE low to SOMI data out
STE disable time
t
STE,DIS
2.2 V, 3 V
50
ns
STE high to SOMI high impedance
2.2 V
20
t
SU,SI
SIMO input data setup time
ns
3 V
15
2.2 V
10
t
HD,SI
SIMO input data hold time
ns
3 V
10
2.2 V
75
110
t
VALID,SO
SOMI output data valid time
UCLK edge to SOMI valid, C
L
= 20 pF
ns
3 V
50
75
30
Specifications
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