MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
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SLAS508J – APRIL 2006 – REVISED JUNE 2015
5.20
Crystal Oscillator, LFXT1 Oscillator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OSCCAPx = 0h, V
CC
= 2.2 V, 3 V
0
OSCCAPx = 1h, V
CC
= 2.2 V, 3 V
10
C
XIN
Integrated input capacitance
(3)
pF
OSCCAPx = 2h, V
CC
= 2.2 V, 3 V
14
OSCCAPx = 3h, V
CC
= 2.2 V, 3 V
18
OSCCAPx = 0h, V
CC
= 2.2 V, 3 V
0
OSCCAPx = 1h, V
CC
= 2.2 V, 3 V
10
C
XOUT
Integrated output capacitance
(3)
pF
OSCCAPx = 2h, V
CC
= 2.2 V, 3 V
14
OSCCAPx = 3h, V
CC
= 2.2 V, 3 V
18
V
IL
Low-level input voltage at XIN
V
CC
= 2.2 V, 3 V
(4)
V
SS
0.2 × V
CC
V
V
IH
High-level input voltage at XIN
V
CC
= 2.2 V, 3 V
(4)
0.8 × V
CC
V
CC
V
(1)
The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(C
XIN
× C
XOUT
) / (C
XIN
+ C
XOUT
). This is independent of XTS_FLL.
(2)
To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
•
Keep the trace between the MCU and the crystal as short as possible.
•
Design a good ground plane around the oscillator pins.
•
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
•
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
•
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
•
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
•
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
(3)
TI recommends external capacitance for precision real-time clock applications; OSCCAPx = 0h.
(4)
Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
5.21
Crystal Oscillator, XT2 Oscillator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
C
XT2IN
Integrated input capacitance
V
CC
= 2.2 V, 3 V
2
pF
C
XT2OUT
Integrated output capacitance
V
CC
= 2.2 V, 3 V
2
pF
V
IL
V
SS
0.2 × V
CC
V
Input levels at XT2IN
V
IH
V
CC
= 2.2 V, 3 V
(2)
0.8 × V
CC
V
CC
V
(1)
The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
(2)
Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
5.22
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
f
USCI
USCI input clock frequency
External: UCLK
f
SYSTEM
MHz
Duty cycle = 50% ±10%
BITCLK clock frequency
f
BITCLK
2.2 V, 3 V
1
MHz
(equals baud rate in MBaud)
2.2 V
50
150
600
t
τ
UART receive deglitch time UART
(1)
ns
3 V
50
100
600
(1)
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
Copyright © 2006–2015, Texas Instruments Incorporated
Specifications
29
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