MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333
www.ti.com
SLAS721D – AUGUST 2010 – REVISED DECEMBER 2015
5.32 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
(see
Figure 5-13
and
Figure 5-14
)
PARAMETER
TEST CONDITIONS
V
CC
MIN
MAX
UNIT
1.8 V
11
PMMCOREV = 0
3 V
8
t
STE,LEAD
STE lead time, STE low to clock
ns
2.4 V
7
PMMCOREV = 3
3 V
6
1.8 V
3
PMMCOREV = 0
3 V
3
t
STE,LAG
STE lag time, Last clock to STE high
ns
2.4 V
3
PMMCOREV = 3
3 V
3
1.8 V
66
PMMCOREV = 0
3 V
50
t
STE,ACC
STE access time, STE low to SOMI data out
ns
2.4 V
36
PMMCOREV = 3
3 V
30
1.8 V
30
PMMCOREV = 0
3 V
23
STE disable time, STE high to SOMI high
t
STE,DIS
ns
impedance
2.4 V
16
PMMCOREV = 3
3 V
13
1.8 V
5
PMMCOREV = 0
3 V
5
t
SU,SI
SIMO input data setup time
ns
2.4 V
2
PMMCOREV = 3
3 V
2
1.8 V
5
PMMCOREV = 0
3 V
5
t
HD,SI
SIMO input data hold time
ns
2.4 V
5
PMMCOREV = 3
3 V
5
UCLK edge to SOMI valid,
1.8 V
76
C
L
= 20 pF,
3 V
60
PMMCOREV = 0
t
VALID,SO
SOMI output data valid time
(2)
ns
UCLK edge to SOMI valid,
2.4 V
44
C
L
= 20 pF,
3 V
40
PMMCOREV = 3
1.8 V
18
C
L
= 20 pF,
PMMCOREV = 0
3 V
12
t
HD,SO
SOMI output data hold time
(3)
ns
2.4 V
10
C
L
= 20 pF,
PMMCOREV = 3
3 V
8
(1)
f
UCxCLK
= 1/2t
LO/HI
with t
LO/HI
≥
max(t
VALID,MO(Master)
+ t
SU,SI(USCI)
, t
SU,MI(Master)
+ t
VALID,SO(USCI)
).
For the master parameters t
SU,MI(Master)
and t
VALID,MO(Master)
, see the SPI parameters of the attached slave.
(2)
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in
Figure 5-13
and
Figure 5-14
.
(3)
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in
Figure 5-13
and
Figure 5-14
.
Copyright © 2010–2015, Texas Instruments Incorporated
Specifications
33
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