Texas Instruments LMH0318, Руководство программиста

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Register Tables
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5.4 Transmitter Registers
Table 8. Transmitter Registers
FIELD REGISTER
REGISTER NAME BITS DEFAULT R/RW DESCRIPTION
ADDRESS
Out0_Mux_Select Reg 0x1C Channel 0x18 OUT0 Mux Selection
7 pfd_sel0_data_mux[2] 0 RW When 0x09[5] = 1'b OUT0 Mux
Selection can be controlled as
6 pfd_sel0_data_mux[1] 0 RW
follows:
pfd_sel0_data_mux[0]
000: Mute
001: 10 MHz Clock
5 0 RW
010: Raw Data
100: Retimed Data
Other Settings - Invalid
vco_clk_sel When 0x09[5] = 1'b and 0x1E[[7:5] =
101'b OUT1 clock selection can be
4 1 RW controlled as follows:
1: OUT1 puts out line rate clock
0: OUT1 puts out 10MHz clock
3 mr_drv_out_ctrl[1] 1 RW Controls both OUT0 and OUT1:
00:
mr_drv_out_ctrl[0]
OUT0: Mute
OUT1: Mute
01:
OUT0: Locked Reclocked Data /
Unlocked Raw Data
OUT1: Locked Output Clock /
Unlocked Mute
2 0 RW
10:
OUT0: Locked Reclocked Data /
Unlocked RAW
OUT1: Locked Reclocked Data /
Unlocked Raw
11:
OUT0: Forced Raw
OUT1: Forced Raw
1 Reserved 0 RW
0 Reserved 0 RW
OUT1_Mux_Select Reg 0x1E Channel 0xE9 OUT1 Mux Selection
7 pfd_sel_data_mux[2] 1 RW When 0x09[5] = 1'b OUT0 Mux
Selection can be controlled as
6 pfd_sel_data_mux[1] 1 RW
follows:
pfd_sel_data_mux[0]
111: Mute
101: 10MHz Clock if reg 0x1c[4]=0
and full rate clock if reg 0x1c[4] = 1
5 1 RW
010: Full Rate Clock
001: Retimed Data
000: Raw Data
Other Settings - Invalid
4 Reserved 0 RW
3 Reserved 1 RW
2 Reserved 0 RW
1 Reserved 0 RW
0 Reserved 1 RW
34 LMH0318 Programming Guide SNLU183 – September 2015
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