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Texas Instruments Jacinto7, Руководство пользователя

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Texas Instruments Jacinto7 Скачать руководство пользователя страница 28

Table 3-6. Board ID Information (continued)

Field Name

Offset /Size

Value

Comments

DDR_TYPE

0038 / 1B (Hex)

0x11

DDR Header Identifier

DDR_LENGTH

0039 / 2B (Hex)

0x2

offset to next header

DDR_CONTROL

003B / 2B (Hex)

0xC560

DDR Control Word
Bit 1:0 = ‘00’ First DDR
Bit 3:2 = ‘00’ No SPD
Bit 5:4 = ‘10’ LPDDR4
Bit 7:6 = ‘01’ 32 bits
Bit 9:8 = ‘01’ 32 bits
Bit 10 = ‘1’ dual rank
Bit 13:11 = ‘000’ Density 64 Gb 
(bit 0 to 3)
Bit 14 = ‘1’ ECC bits present 
(inline, not separate bits)
Bit 15 = ‘1’ Density 64 Gb (bit 4)

DDR_TYPE

003D / 1B (Hex)

0x11

DDR Header Identifier

DDR_LENGTH

003E / 2B (Hex)

0x2

offset to next header

DDR_CONTROL

0040 / 2B (Hex)

0xC560

DDR Control Word

DDR_TYPE

0042 / 1B (Hex)

0x11

DDR Header Identifier

DDR_LENGTH

0043 / 2B (Hex)

0x2

offset to next header

DDR_CONTROL

0045 / 2B (Hex)

0xC560

DDR Control Word

DDR_TYPE

0047 / 1B (Hex)

0x11

DDR Header Identifier

DDR_LENGTH

0048 / 2B (Hex)

0x2

offset to next header

DDR_CONTROL

004A / 2B (Hex)

0xC560

DDR Control Word

END_LIST

0111 / 1B (Hex)

0xFE

End Marker

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

December 2022

*

Initial Release

Revision History

www.ti.com

28

Jacinto7 TDA4VE-Q1/TDA4VL-Q1/TDA4AL-Q1 Evaluation Module (EVM)

SPRUJ69 – DECEMBER 2022

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Copyright © 2022 Texas Instruments Incorporated

Содержание Jacinto7

Страница 1: ...commended External Power Supply 9 Table 2 2 Power Domain Status 9 Table 2 3 Power Allocation 9 Table 2 4 Dip Switch SW3_CP SW13_CP EVM Configuration Settings 10 Table 2 5 EVM Configuration Switch Function 10 Table 2 6 Dip Switch SW9 Configuration for MCU_BOOTMODE 11 Table 2 7 Dip Switch SW8 Configuration for BOOTMODE 11 Table 2 8 Reset Pushbuttons 11 Table 2 9 User Pushbuttons and LEDs 11 Table 2 ...

Страница 2: ...e 3 5 Power management IC s 26 Table 3 6 Board ID Information 27 Table of Contents www ti com 2 Jacinto7 TDA4VE Q1 TDA4VL Q1 TDA4AL Q1 Evaluation Module EVM SPRUJ69 DECEMBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Страница 3: ...ort Information The Jacinto7 Common Processor Board CPB kit includes Common Processor Board with mounted Quad Ethernet Adapter USB A to USB micro B Cable 2x USB A to USB C Cable Ethernet Cable 2x Display Port Cable 2 5mm Power Cable with Wire Leads The orderable part numbers are provided in table below TDA4VE Q1 TDA4VL Q1 TDA4AL Q1 System On Module J721S2XSOMG01EVM Jacinto7 Common Processor Board ...

Страница 4: ...n the area of the heatsink Caution Caution Hot surface Contact may cause burns Do not touch 1 4 Reach Compliance In compliance with the Article 33 provision of the EU REACH regulation we are notifying you that this EVM includes one or more components containing at least one Substance of Very High Concern SVHC above 0 1 These uses from Texas Instruments do not exceed 1 ton per year The SVHC s are l...

Страница 5: ...identify the key user interfaces on the EVM top and bottom view www ti com User Interfaces SPRUJ69 DECEMBER 2022 Submit Document Feedback Jacinto7 TDA4VE Q1 TDA4VL Q1 TDA4AL Q1 Evaluation Module EVM 5 Copyright 2022 Texas Instruments Incorporated ...

Страница 6: ...DA4AL Q1 System on Module Component Identification User Interfaces www ti com 6 Jacinto7 TDA4VE Q1 TDA4VL Q1 TDA4AL Q1 Evaluation Module EVM SPRUJ69 DECEMBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Страница 7: ...www ti com User Interfaces SPRUJ69 DECEMBER 2022 Submit Document Feedback Jacinto7 TDA4VE Q1 TDA4VL Q1 TDA4AL Q1 Evaluation Module EVM 7 Copyright 2022 Texas Instruments Incorporated ...

Страница 8: ... using an external power supply or power accessory which complies with applicable regional safety standards such as UL CSA VDE CCC PSE etc 2 2 Power Input J7_CP with LED for Status LD2_CP LD3_CP This EVM supports a wide input range of 6 5V to 28V There is a DC Jack provided for power input The exact power required for the EVM is largely dependent on the application and connected peripherals The re...

Страница 9: ...ed OFF 1 LD5 MAIN domain of the EVM is powered MAIN domain of the EVM is not powered OFF 1 1 The power management IC PMIC includes functions to monitor power domains including over under voltage over current and residual voltage If the PMIC detects and error it may transition to safe mode where it powers down both the MCU and MAIN domains 2 2 2 Power Budget Considerations The exact power required ...

Страница 10: ... J7AEP SOM SW3 9 ON EVM Configuration EEPROM Write Protection Sets EVM s configuration EEPROM Write Protection 0 OFF Configuration EEPROM can be updated 1 ON Configuration EEPROM cannot be updated protected SW3 10 ON User Defined User Define maps to IO Expander Input 0 OFF User Defined 1 ON User Defined SW13 1 OFF Reserved Test Mode Wait Reset Reserved must set to 0 OFF for normal EVM operation on...

Страница 11: ...3 Reset Pushbuttons SW7_CP SW6_CP SW5_CP SW4_CP When pressed the specific EVM domain is issued a reset and is held in reset until the button is released Table 2 8 Reset Pushbuttons Push Button Domain Function Description SW7 All Power On Reset Power On Cold Reset for EVM resets both processor domains MCU MAIN and all EVM peripherals SW5 MCU MCU Warm Reset Warm reset for MCU domain SW4 MAIN Power O...

Страница 12: ...Com Port s to be used with any terminal application Virtual Com Port drivers for the transceiver s can be obtained from https www ftdichip com Products ICs FT2232H html https www ftdichip com Products ICs FT4232H html Once installed the Host PC will create the Virtual Com Ports two ports for FT2232 4 ports for FT4232 Depending on the other Host PC resources available the Com Ports may not be locat...

Страница 13: ...B development 2 4 5 PCIe Card Slot J8_CP One lane of PCIe Gen3 is supported on the EVM The Common Processor board supports two PCIe slots however only one PCIe slot J8 is supported with processor module The second PCIe connector is unused The REFCLK is automatically generated on board 2 4 6 Display Port Interfaces J36_CP J37_CP The EVM supports two DisplayPort panels via standard DP cables interfa...

Страница 14: ...5 1 Heatsink ACC3_SOM with Fan Header J15_CP The heatsink supports cooling of the device at ambient temperatures If your environment or use case requires additional cooling a fan can be added to the heatsink The fan connector is a 3 pin header 440054 3 from TE Connectivity and supports 12VDC fans Mating connector is 440129 3 and 1735801 1 Table 2 12 Fan Header Pin Definition J15 Pin Pin Name Descr...

Страница 15: ...to two CSI2 interfaces The bandwidth of each CSI2 interface is 10Gbps 4 data lanes each up to 2 5Gbps The expansion connector also includes power and other IO for communicating with the capture devices All control signals are configurable for 3 3 V or 1 8 V IO voltage levels See Section 2 3 1 for configuration details Table 2 15 High Speed Camera Expansion Pin Definition J52 Pin Pin Name Descripti...

Страница 16: ...SIb_D2_P CSI Port 1 Open Input 38 Power Power IO Level 1 8 V or 3 3 V Output 39 CSIb_D2_N CSI Port 1 Open Input 40 Power Power IO Level 1 8 V or 3 3 V Output Note In the DIR column output is to the expansion module input is from the expansion module Bi Dir signals can be configured as either input or output 2 5 4 Automation and Control Connector J50_CP The EVM supports an interface to allow for au...

Страница 17: ...t details 2 5 6 CSI TX J10_SOM The J7AEP SOM Board in the EVM includes a 40 pin 2x20 0 5 mm pitch high speed camera transmit interface J10 The expansion connector supports a single CSI2 TX 4Lane interface The interface is designed for internal testing and may not include all the required power signals for interfacing with a display See schematic for connector pinout details 2 5 7 Accessory Power C...

Страница 18: ...EVM Functional Block diagram Circuit Details www ti com 18 Jacinto7 TDA4VE Q1 TDA4VL Q1 TDA4AL Q1 Evaluation Module EVM SPRUJ69 DECEMBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Страница 19: ... Connector J52 QSH 020 01 L D DP A K Display Port DP0 DSI1 Texas Instruments SN65DSI86IPAPQ1 ADC Header MCU_ADC0 MCU_ADC1 1 MCU_OSPI0 is connected to two different flash memories target memory selected via a mux 3 3 I2C Address Mapping Table 3 2 shows the complete I2C address mapping details on the EVM Table 3 2 I2C Mapping Table Connected Peripheral Processor Resources J7AEPComponent Part Number ...

Страница 20: ...h for Automation header I2C1 0x22 Texas Instruments TCA6424ARGJR Current Monitors and Header I2C1 0x40 to 0x4F Texas Instruments INA226AIDGSR 8bit GPIO Expander3 I2C3 0x20 Texas Instruments TCA6408ARGTR FPD Link iii Deserializer I2C3 0x2C Texas Instruments DS90UB926Q Q1 AUDIO IF Codec I2C3 0x44 Texas Instruments PCM3168A Q1 I2C IO Expander I2C5 0x41 Texas Instruments PCA9536DGKR Expansion Camera I...

Страница 21: ...SPI 1 No interrupt default WKUP_GPIO0_3 MCU Ethernet Interrupt Input 0 Interrupt pending 1 Normal operation default WKUP_GPIO0_55 System Power Down Output 0 normal operation default 1 system power down WKUP_GPIO0_69 MCU CAN0 Standby Output 0 Normal Mode 1 Standby Mode default WKUP_GPIO0_57 Interrupt from I3C Gyroscope sensor Input 0 Interrupt pending 1 Normal operation default WKUP_GPIO0_70 Push b...

Страница 22: ...e Output 0 DisplayPort Transmitter is disabled default 1 DisplayPort Transmitter is enabled P06 Expansion Board Specific Bi Dir 0 LIN Bus PHY is Disabled default 1 LIN Bus PHY is Enabled P07 Standby signals for CAN Transceivers Output 0 Normal Mode 1 Standby Mode default I2C5 TCA6408 Addr 0x20 Function DIR Level Remarks P00 Camera Expansion Reset 1 and 2 Output 0 Camera Expansion is disabled Reset...

Страница 23: ...0 Reset is NOT asserted Reserved P06 PCIe0 PERSTz Output Root Complex Mode Output 0 PCIe0 Reset is asserted 1 PCIe0 Reset is NOT asserted Reserved P07 PCIe0 PERSTz to PORz End Point Mode Output 0 PCIe0 PERSTz is separate from PORz 1 PCIe0 PERSTz can control PORz Reserved P10 PCIe1 Card Presence Detection Input 0 Card detected for PCIe1 1 Card NOT detected for PCIe1 default P11 PCIe0 Card Presence ...

Страница 24: ... Default is set via dip switch SW3 bits 3 4 P05 USB Type C Mode Selection 2 Input P06 ENABLE signal to MCAN3 Phy Output MCAN3 PHY Enable 0 device disabled 1 normal operation P07 Standby signals for MCAN3 Transceivers Output MCAN3 PHY Standby 0 device standby 1 normal operation P10 Power Measurement Bus Enable Output 0 Enabled access to INA from processor I2C1 default 1 Disables access to INA from ...

Страница 25: ... is ON 1 LED LD9 is OFF default P27 User LED LD8 Output 0 LED LD8 is ON 1 LED LD8 is OFF default I2C3 TCA6408 Addr 0x20 Function DIR Level Remarks P00 Audio Codec Enable Reset Output 0 Audio Codec is disabled Reset default 1 Audio Codec is enabled active P01 Reserved Unused Bi Dir Reserved Unused P02 RESET to UB926 Output Reserved UB926 is not supported P03 UB926 PLL lock status Input Reserved UB9...

Страница 26: ... s Bus 1 Address Power Rail Nom V Shunt Value Bus 2 Address Power Rail Nom V Shunt Value 0x40 Processor MCU VDD VDD_MCU_0V 85 0 85 10m ohm 0x40 Processor IO at 1 8V VDD_IO_1V8 1 8 10m ohm 0x41 Processor MCU VDD VDD_MCU_RA M_0V85 0 85 10m ohm 0x41 Processor IO at 3 3V VDD_IO_3V3 3 3 10m ohm 0x42 VDA_MCU_1V 8 1 8 10m ohm 0x42 Processor Dual Voltage IO VDD_SD_DV 3 3 1 8 10m ohm 0x43 Processor MCU IO ...

Страница 27: ...red in an on board EEPROM The first 259 bytes of the memory are pre programmed with EVM identification information The format of the data is provided in Table 3 6 The remaining bytes are available to user defined storage Table 3 6 Board ID Information Field Name Offset Size Value Comments MAGIC 0000 4B Hex 0xEE3355AA Header Identifier M_TYPE 0004 1B Hex 0x01 Fixed length and variable position boar...

Страница 28: ...t to next header DDR_CONTROL 0040 2B Hex 0xC560 DDR Control Word DDR_TYPE 0042 1B Hex 0x11 DDR Header Identifier DDR_LENGTH 0043 2B Hex 0x2 offset to next header DDR_CONTROL 0045 2B Hex 0xC560 DDR Control Word DDR_TYPE 0047 1B Hex 0x11 DDR Header Identifier DDR_LENGTH 0048 2B Hex 0x2 offset to next header DDR_CONTROL 004A 2B Hex 0xC560 DDR Control Word END_LIST 0111 1B Hex 0xFE End Marker 4 Revisi...

Страница 29: ...o change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you will fully indemn...

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