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Table 3-4. GPIO Mapping for Expansion IO (continued)
I2C0/TCA6416 Addr: 0x21 Function Input/Output Remarks
P00 PCIe1 mode selection Input
0’ – Processor/PCIe1 is Root
Complex
‘1’ – Processor/PCIe1 is End
Point
(Note Default is set via dip
switch)
P01 PCIe1 PERSTz status Input
0’ – PCIe1 Reset is asserted
‘1’ – PCIe1 Reset is NOT
asserted
P02
PCIe1 PERSTz Output
(Root Complex Mode)
Output
‘0’ – PCIe1 Reset is asserted
‘1’ – PCIe1 Reset is NOT
asserted
P03
PCIe1 PERSTz to PORz
(End Point Mode)
Output
0’ – PCIe1 PERSTz is separate
from PORz
‘1’ – PCIe1 PERSTz can control
PORz
P04 PCIe0 mode selection Input
0’ – Processor/PCIe0 is Root
Complex
‘1’ – Processor/PCIe0 is End
Point
(Note Default is set via dip
switch) (Reserved)
P05 PCIe0 PERSTz status Input
0’ – PCIe0 Reset is asserted
‘1’ – PCIe0 Reset is NOT
asserted (Reserved)
P06
PCIe0 PERSTz Output
(Root Complex Mode)
Output
‘0’ – PCIe0 Reset is asserted
‘1’ – PCIe0 Reset is NOT
asserted (Reserved)
P07
PCIe0 PERSTz to PORz
(End Point Mode)
Output
0’ – PCIe0 PERSTz is separate
from PORz
‘1’ – PCIe0 PERSTz can control
PORz(Reserved)
P10 PCIe1 Card Presence Detection Input
‘0’ – Card detected for PCIe1
‘1’ – Card NOT detected for
PCIe1 (default)
P11 PCIe0 Card Presence Detection Input
0’ – Card detected for PCIe0
‘1’ – Card NOT detected for
PCIe0 (default)(Reserved)
P12 External Clock enabled for PCIe0 Output
0’ – External Clock is NOT
enabled for PCIe0
‘1’ – External Clock is enabled for
PCIe0 (default)(Reserved)
P13 External Clock enabled for PCIe1 Output
0’ – External Clock is NOT
enabled for PCIe1
‘1’ – External Clock is enabled for
PCIe1 (default)
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SPRUJ69 – DECEMBER 2022
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Jacinto7 TDA4VE-Q1/TDA4VL-Q1/TDA4AL-Q1 Evaluation Module (EVM) 23
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