Texas Instruments GC5325, Руководство пользователя

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Appendix A LEDs, Switches, Connectors, and Jumpers
A.1 TSW3100 LED, Switches, and Connectors
Power and status LEDs on after power is applied:
D3 – 2.5 V present
D4 – 1.8 V present
D5 – 1.2 V present
D6 – 3.3 V present
D11 – FPGA configured
D13 – Pattern Generator Idle
D19 – DDR2 PLL Lock
D20 – NIOS PLL Lock
D23 – +1.8 Vdc and +3.3 Vdc external power supply ON
Status LEDs ON after pattern is loaded successfully
D13 – Pattern Generator Idle
D14 – Pattern Generator CLK present
D15 – Pattern Generator Running
D16 – FIFO Empty Error
D17 – FIFO Full Error
D18 – LVDS PLL Lock
D19 – DDR2 PLL Lock
D20 – NIOS PLL Lock
D21 – CMOS Mode
D24 – LVDS Mode
Table 1. TSW3100 Jumper and Switch Description
Designator Description Default Position
J50 Clock select. 2-3 for onboard oscillator. 1-2 for SMA J41 2-3
SW2 Sets Ethernet address and invert option for CMOS output clock. See TSW3100 User ' s All set to " Open "
Guide for more information
SW1 Board main power switch " ON "
SW5 External 1.8-Vdc and 3.3-VDC output supply. Not used with the GC5325SEK " OFF "
S9 FPGA Config. Press to reload FPGA configuration prom code into the FPGA
S8 Spare Not Used
S7 Start/Stop. Used to stop and re-start pattern generator. See TSW3100 User ' s Guide for
more information
S3 Sync. Sends a one-time Sync pulse at the start of the test pattern
Table 2. TSW3100 Connectors
Designator Description Default Position
J63 Baseband connector for GC5325 Connect to GC5325 EVM J1
J64 Baseband connector for GC5325 Connect to GC5325 EVM J3
J73 CMOS baseband CLK input from GC5325 Connect to GC5325 SMA J2
J13 Ethernet connection to PC for pattern load Connect to Host PC via
USB-Ethernet adapter
J9 Power input connector from GC5325 Connect to GC5325 J22
29 SLWU063F – April 2009 – Revised April 2011 LEDs, Switches, Connectors, and Jumpers
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