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Technical Reference Manual

 

 

TMDXEVM6657L 

SPRUHG7 - Revised August 2012    

                                                            TMDXEVM6657LE 

 

 

 

 

 

 

 

Page 65 / 90 

VCC_5V_EN 

O 

5V  Voltage  Power  Supply  Enable:

  Enable  for  5V 

power rail. 

SYS_PGOOD 

O 

System Power Good Indication:

 Asserted by FPGA 

to system when all power supplies are valid. 

Clock Configuration 

CLOCK2_SSPCS1 

O 

SPI  Chip  Select  Enable:

  Connected  to  Clock 

Generator  SPI_LE  pin.  Falling  edge  of  SSPCS1 
initiates  a  transfer.  If  SSPCS1  is  high,  no  data 
transfer can take place. 

CLOCK2_SSPCK 

O 

SPI  Serial  Clock:

  Connected  to  Clock  Generator 

SPI_CLK  pin.  FPGA  SPI  bus  clocks  data  in  and  out 
on  the  rising  edge  of  SSPCK.  Data  transitions 
therefore occur on the falling edge of this clock. 

CLOCK2_SSPSI 

O 

SPI  Serial  Data  MOSI:

  Connected  to  Clock 

Generator  MOSI  pin.  This  signal  is  used  for  serial 
data  transfers  from  master  (FPGA)  output  to  slave 
(CDCE62005) input. 

CLOCK2_SSPSO 

I 

PU 

SPI  Serial  Data  MISO:

  Connected  to  Clock 

Generator MISO pin. This signal is used for the serial 
data  transfers  from  slave  (CDCE62005)  output  to 
master (FPGA) input. 

REFCLK2_PD# 

O 

CLOCK  Generator  Power  Down: 

Places  Clock 

Generator  into  power  down  state  forcing  the 
differential clock output into high-impedance state. 

UCD9222 Interface : 

UCD9222_PG1 

I 

UCD9222  Power  Good  Indication  for  CVDD  DSP 
Core Power: 

Indicates that CVDD DSP core power is 

valid. 

UCD9222_ENA1 

O 

UCD9222  Enable  for  CVDD  DSP  Core  Power: 

Enables CVDD DSP core power rail. 

UCD9222_PG2 

I 

UCD9222 Power Good Indication for VCC1V0 DSP 
Core  Power: 

Indicates  that  VCC1V0  DSP  core 

power is valid. 

UCD9222_ENA2 

O 

UCD9222  Enable  for  CVDD  DSP  Core  Power: 

Enables VCC1V0 DSP core power rail. 

PGUCD9222 

I 

UCD9222  Power  Good  Indication:

  Indicates  both 

DSP core supplies - CVDD and VCC1V0 are valid. 

UCD9222_RST# 

O 

UCD9222  Reset:

  An  active  low  signal  will  reset 

UCD9222 device. 

PM BUS : (RFU) 

PMBUS_CLK 

O 

PM  Bus  Clock:

  FPGA  provided  clock  source  on  PM 

bus. 

PMBUS_DAT 

I/O 

PM  Bus  Data:

  A  PM  Bus  slave  device  can  receive 

data  provided  by  master  (FPGA),  or  it  can  also 
provide data to master (FPGA) via this signal line. 

PMBUS_ALT 

I 

PM Bus Alert:

 A PM Bus device may notify the host 

(FPGA) via this signal if a fault or warning is detected. 

PMBUS_CTL 

I 

PU 

PM  Bus  Control:

  Used  to  turn  on/off  the  device  in 

conjunction  with  UCD9222_ENA1  /  UCD9222_ENA2 
pins. 

PHY Interface : 

PHY_INT# 

I 

Interrupt Request from 88E112 PHY (RFU) 

Содержание eInfochips TMDXEVM6657L

Страница 1: ...LE Technical Reference Manual Version 1 1 Literature Number SPRUHG7 Revised August 2012 Document Copyright Publication Title C6657 Lite EVM Technical Reference Manual All Rights Reserved Reproduction...

Страница 2: ...local regulatory requirements including but not limited to Food and Drug Administration regulations UL CSA VDE CE RoHS and WEEE that relate to your use and that of your employees contractors or design...

Страница 3: ...isplays are shown in a mono spaced font Examples use bold for emphasis and interactive displays use bold to distinguish commands that you enter from items that the system displays such as prompts comm...

Страница 4: ...Code Explorer DSP BIOS RTDX Online DSP Lab TMS320 TMS320C54x TMS320C55x TMS320C62x TMS320C64x TMS320C67x TMS320C5000 and TMS320C6000 MS DOS Windows Windows XP and Windows NT are trademarks of Microsof...

Страница 5: ...VM Evaluation Module FPGA Field Programmable Gate Array I2C Inter Integrated Circuit IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface JTAG Joint Test Action Grou...

Страница 6: ...7L 24 2 4 2 JTAG TMDXEVM6657LE 25 2 4 2 1 XDS560V2 MEZZANINE EMULATOR BOOTING 26 2 5 CLOCK DOMAINS 27 2 6 I2C BOOT EEPROM SPI NOR FLASH 28 2 7 FPGA 29 2 8 ETHERNET SWITCH 30 2 9 SERIAL RAPIDIO SRIO IN...

Страница 7: ...TEST_PH1 EXPANSION HEADER EMIF 16 SPI GPIO TIMER I O I2C MCBSP AND UART 46 3 2 14 USB1 MINI USB CONNECTOR 47 3 3 DIP AND PUSHBUTTON SWITCHES 48 3 3 1 RST_COLD1 COLD RESET 48 3 3 2 RST_FULL1 FULL RESE...

Страница 8: ...BOOT 71 5 4 RESET DEFINITION 71 5 4 1 RESET BEHAVIOR 71 5 4 2 RESET SWITCHES AND TRIGGERS 71 5 5 SPI PROTOCOL 72 5 5 1 FPGA DSP SPI PROTOCOL 72 5 5 2 FPGA CDCE62005 CLOCK GENERATOR SPI PROTOCOL 74 5...

Страница 9: ...TOP VIEW 37 FIGURE 3 2 C6657 LITE EVM BOARD LAYOUT BOTTOM VIEW 38 FIGURE 3 3 COM_SEL1 JUMPER SETTINGS 41 FIGURE 3 4 HYPERLINK CONNECTOR 43 FIGURE 3 5 SW3 DEFAULT SETTINGS 48 FIGURE 3 6 SW5 DEFAULT SET...

Страница 10: ...PIN OUT 43 TABLE 3 9 J4 CONNECTOR PIN OUT 44 TABLE 3 10 J5 CONNECTOR PIN OUT 44 TABLE 3 11 ETHERNET CONNECTOR PIN OUT 44 TABLE 3 12 PMBUS CONNECTOR PIN OUT 45 TABLE 3 13 FPGA JTAG HEADER PIN OUT 45 T...

Страница 11: ...development process and to reduce the time to market The key features of the C6657 Lite EVM are Texas Instruments fixed point DSP TMS320C6657 512 Mbytes of DDR3 Memory up to 1024Mbytes supported 128...

Страница 12: ...0 16 DSP SPI DSP GPIO JTAG Pwr Seq Ctrl Clk Gen CDCE62005 JTAG TSW 108 07 S S Boot Config PCIESSEN User Switch SYSPG_LED Debug LED x 4 Clk_SPI DIP SW x 3 GPIO McBSP_AMC_EN DSP Rst Int Ctrl ON BOARD P...

Страница 13: ...CLKP N 100 0MHz Core CLKP N 66 67MHz DDR3 CLKP N 48 0MHz FPGA 25 0MHz Ethernet 12 0MHz FT2232HL 32 768kHz MSP430 AMC_JTAG 5 0V HyperLink CONN 768670011 16MB NOR Flash N25Q032A11ESE40F Multiplexer IDT5...

Страница 14: ...all the necessary development tools drivers and documentation To start operating the board follow instructions in the Quick Start Guide This guide provides instruction for proper connections and confi...

Страница 15: ...TMDXEVM6657LE 1 4Boot Mode and Boot Configuration Switch Setting The C6657 Lite EVM has 18 sliding DIP switches Board Ref SW3 SW5 and SW9 to determine boot mode boot configuration device number Endia...

Страница 16: ...R3 buffers of DSP HyperLink SRIO SGMII PCIe SERDES regulators in DSP and DDR3 DRAM chips 1 8V is used for DSP PLLs DSP LVCMOS I Os and FPGA I Os driving the DSP 2 5V is used for Gigabit Ethernet PHY c...

Страница 17: ...EEPROM SPI NOR Flash 2 7 FPGA 2 8 Gigabit Ethernet PHY 2 9 Serial RapidIO SRIO Interface 2 10 DDR3 External Memory Interface 2 11 16 bit Asynchronous External Memory Interface or UPP 2 12 HyperLink I...

Страница 18: ...Technical Reference Manual TMDXEVM6657L SPRUHG7 Revised August 2012 TMDXEVM6657LE Page 18 90 Table 2 1 TMS320C6657 Memory Map...

Страница 19: ...Technical Reference Manual TMDXEVM6657L SPRUHG7 Revised August 2012 TMDXEVM6657LE Page 19 90...

Страница 20: ...Technical Reference Manual TMDXEVM6657L SPRUHG7 Revised August 2012 TMDXEVM6657LE Page 20 90...

Страница 21: ...Technical Reference Manual TMDXEVM6657L SPRUHG7 Revised August 2012 TMDXEVM6657LE Page 21 90...

Страница 22: ...mation on DSP supported Bootmode refer TMS320C6657 Datasheet and C66x Boot Loader User Guide Table 2 2 Boot Configuration Selection DIP Switch DSP GPIO BM Primary Function Selection SW3 Pin 1 ENDIANES...

Страница 23: ...revision are located below RJ 45 Jack in bottom silk as shown in Figure 2 1 Table 3 describes the PCA PCB revisions Figure 2 1 EVM Board Revision Table 2 3 PCA PCB revision description PCA Rev PCB Rev...

Страница 24: ...on to DSP however when external emulator is connected to EVM board circuitry switches automatically to give DSP s emulation access to external emulator When on board emulator and external emulator bot...

Страница 25: ...cable needs to be connected to the mini AB connector J1 on XDS560v2 Mezzanine Emulator and not to mini B connector J11 on the main board For TMDXEVM6657LE the mini B connector J11 on the main board ca...

Страница 26: ...wing LEDs sequence Green LED D3 turns ON Yellow LED D2 and Red LED D1 turns ON Green LED D3 blinks and turns OFF After the completion of booting XDS560v2 mezzanine emulator is ready to interface with...

Страница 27: ...LK McBCP_Tx_CLK McBCP_SL_CLK McBCP_FSR McBCP_FST 2 2 2 2 TCLKA from AMC TCLKB NU from AMC TCLKC from AMC TCLKD from AMC TCLKB TEST HDR 80pins McBCP_Rx_CLK McBCP_Tx_CLK McBCP_SL_CLK McBCP_FSR McBCP_FST...

Страница 28: ...on procedure and the bank at 0x51 contains the second level boot loader program The second level boot loader can be used to either run the POST program or launch the OOB demonstration from NOR flash m...

Страница 29: ...657 DSP_RESET DSP_LRRESETNMIEN DSP_RESETFULL DSP_CORESEL 1 0 DSP_NMI DSP_HOUT DSP_SYSCLKOUT DSP_LRESET DSP_BOOTCOMPLETE SPI_FPGA_MISO SPI_FPGA_SCK SPI_FPGA_CS1 SPI_FPGA_MOSI DSP_McBSP 1 0 _TXCLK DSP_M...

Страница 30: ...and Ethernet PHY PHY1 DSP C6657 SGMII MDIO MDC Eth PHY 88E1112 MDI S_Px F_Px I2C MDIO 2 LVL TXL PCA9306 2 5V 2 1 8V 2 SGMII 4 2KB EEPROM 24LC02B I ST 10 100 1000Mbps 4 10 100 1000Mbps 8 AMC CON Fiber...

Страница 31: ...657 Figure 2 7 C6657 Lite EVM SRIO Port Connections 2 10 DDR3 External Memory Interface The C6657 Lite EVM DDR3 interface connects to two 2Gbit 128Meg x 16 DDR3 1600 devices This configuration allows...

Страница 32: ...Lite EVM The EMIF16 module provides an interface between DSP and asynchronous external memories such as NAND and NOR flash Micron MT29F1G08ABCHC is used on board For more information see External Memo...

Страница 33: ...ock signal For more information see Hyperlink Interface for KeyStone Devices User Guide The figure below shows Hyperlink bus connections on the C6657 Lite EVM RX 3 0 DSP C6657 HyperLink CON IPASS HD T...

Страница 34: ...red clocks and frame syncs If this signal goes high these clocks and syncs are tri stated and McBSP is accessed over 80 pin header For more information see the McBSP User Guide for the C6657 DSP The f...

Страница 35: ...ate Hi Z i e no drive McBSP accessed over 80 Pin header 2 15 UART Interface The C6657 has two UART ports UART0 and UART1 UART1 is directly connected to 80 pin expansion header while a serial port is p...

Страница 36: ...MC base specification Both of these LEDs will blink as part of initialization process when the MMC will receive management power Blue LED D2 Blue LED will turn ON when MicroTCA chassis is powered ON a...

Страница 37: ...d and its connectors switches and test points It contains 3 1 Board Layout 3 2 Connector Index 3 3 Switches 3 4 Test Points 3 5 System LEDs 3 1Board Layout The C6657 Lite EVM board dimension is 7 11 x...

Страница 38: ...nector AMC1 170 AMC Edge Connector COM1 3 UART 3 Pin Connector COM_SEL1 6 UART Route Select Jumper DC_IN1 3 DC Power Input Jack Connector EMU1 60 TI 60 Pin DSP JTAG Connector HyperLink1 36 HyperLink c...

Страница 39: ...Pin Signal Description Pin Signal Description 1 GND Ground Signal 170 GND Ground Signal 2 VCC12 12V Power 169 AMC_JTAG_TDI JTAG Data In 3 PS1 Presence 1 168 AMC_JTAG_TDO JTAG Data Out 4 MP Management...

Страница 40: ...51 AMCC_P5_PCIe_TX1N PCIe Port 1 TX 120 NC 52 GND Ground Signal 119 GND Ground Signal 53 AMCC_P5_PCIe_RX1P PCIe Port 1 RX 118 NC 54 AMCC_P5_PCIe_RX1N PCIe Port 1 RX 117 NC 55 GND Ground Signal 116 GN...

Страница 41: ...the PC Table 3 4 UART Connector pin out Pin Signal Name 1 Ground 2 Transmit 3 Receive 3 2 4 COM_SEL1 UART Route Select Connector UART port can be accessed either through Mini USB connector USB1 or thr...

Страница 42: ...connects with the DSP The I O voltage level on these pins is 1 8V So any 1 8V level compatible emulator can be used to interface with the C6657 DSP It should be noted that when an external emulator i...

Страница 43: ...le 1110670200 can be used to connect two EVMs together Figure 3 4 HyperLink Connector Table 3 8 DSP JTAG Connector pin out Pin Signal Name Pin Signal Name A1 HyperLink_TXFLCLK B1 HyperLink_RXPMDAT A2...

Страница 44: ...J4 Connector pin out Pin Signal Name 1 VCC3V3_AUX thru PU 2 Ground Table 3 10 J5 Connector pin out Pin Signal Name 1 VCC3V3_AUX 2 Ground thru PD 3 2 9 LAN1 Ethernet Connector LAN1 is a Gigabit RJ45 E...

Страница 45: ...3 PMBUS_ALT 4 PMBUS_CTL 5 Gnd 3 2 11 TAP_FPGA1 FPGA JTAG Connector For Factory Use Only TAP_FPGA1 is an 8 pin JTAG connector for the FPGA programming and the PHY boundary test of the factory only The...

Страница 46: ...22 DSP_EMIFA10 UPPXD10 EMIF Addr10 23 DSP_EMIFD08 UPPD08 EMIF Data8 24 DSP_EMIFA11 UPPXD11 EMIF Addr11 25 DSP_EMIFD09 UPPD09 EMIF Data9 26 DSP_EMIFA12 UPPXD12 EMIF Addr12 27 DSP_EMIFD10 UPPD10 EMIF D...

Страница 47: ...PCK SPI clock 70 DSP_McBSP1_FSR McBSP Frame Sync Receive 1 71 DSP_UART1_TX UART Data Out 72 DSP_McBSP1_FST McBSP Frame Sync Transmit 0 73 DSP_UART1_RX UART Data In 74 DSP_McBSP1_RX McBSP Data In 1 75...

Страница 48: ...future use 3 3 2 RST_FULL1 Full Reset Pressing the RST_FULL1 button switch will issue a RESETFULL to TMS320C6657 by FPGA It ll reset DSP and other peripherals 3 3 3 RST_WARM1 Warm Reset Pressing the...

Страница 49: ...he positions and corresponding function on SW5 Table 3 19 SW4 DSP Boot Mode Selection Switch SW5 Position Description Default Value Function 4 1 Boot Mode 3 0 0001 Boot mode selection pins for DSP Mas...

Страница 50: ...PRUHG7 Revised August 2012 TMDXEVM6657LE Page 50 90 3 4Test Points The C6657 Lite EVM Board has 38 test points The position of each test point is shown in the figure below Figure 3 7 Board Test Points...

Страница 51: ...P25 5 0 Supply TP27 1 5V Supply TP28 1 2V Supply TP22 1 8V AUX Supply TP20 2 5V Supply TP21 1 8V Supply TP24 0 75V Supply 3 5System LEDs The C6657 Lite EVM board has eight LEDs Their positions on the...

Страница 52: ...SPRUHG7 Revised August 2012 TMDXEVM6657LE Page 52 90 Figure 3 9 Board LEDs Additional LEDs on TMDXEVM6657LE board are highlighted in figure below and their description is listed in table 3 22 Figure 3...

Страница 53: ...EDs LED Color Description D1 Activity LED 1 Red ON DTC Ready OFF DTC Not Ready D2 Activity LED 2 Yellow ON FPGA Programmed OFF FPGA Not Programmed D3 Activity LED 3 Green Reserved D4 Status LED 3 Gree...

Страница 54: ...hout ECC PHY 3 07W USB 0 86W Misc 1 23W XDS560v2 Mezzanine if used 4 2W Total EVM Board Consumption is 22 18W approx Hence the selected AC DC 12V adapter should be rated for a minimum of 22 5 Watts Ta...

Страница 55: ...Power MMC MPS430 VCC3V3_MP 3 30V 0 048A 1 0 16W 0 16W MMC Power FPGA VCC1V2 1 20V 0 125A 1 0 15W 0 59W FPGA Core Power VCC3V3_AUX 3 30V 0 024A 1 0 08W FPGA 3 3V bank I O Power VCC1V8_AUX 1 80V 0 200A...

Страница 56: ...support all control sequencing and boot logic The Auxiliary Power rails contain VCC3V3_AUX VCC1V8_AUX VCC1V2 VCC5 The maximum allowable power is 22 5W from the external AC brick supply or from the 8 A...

Страница 57: ...llowed by explanations of critical component selection CVDD AVS core power for TMS320C6657 VCC1V0 1 0V fixed core power for TMS320C6657 VCC3V3_AUX 3 3V power for peripherals VCC1V5 1 5V DDR3 power for...

Страница 58: ...1 900kHz 0 0825 2 69uF Cout min2 1 8 fsw Iripple Vripple 1 8 900kHz 0 3 0 033 1 26uF Reference Capacitor 22uF 100nF Inductor Calculation L Vin max Vout Iout Kind Vout Vin max Fsw 12 5 3 3 3 0 3 3 3 1...

Страница 59: ...s are identified below The TMS320C6657 DSP requires specific power up and power down sequencing Figure 4 2 and Figure 4 3 illustrate the proper boot up and down sequence Table 4 3 provides specific ti...

Страница 60: ...ting OE pin 9 RESETz Other reset and NMI pins 5ms De asserts RESETz and unlocks other reset and NMI pins for DSP after VCC0V75 is stable and CDCE62005 PLL locked for 5ms In the meanwhile FPGA will dri...

Страница 61: ...zzanine Card VCC2V5 Eth PHY UCD9222_ENA1 CVDD1 DSP UCD9222_ENA2 VCC1V0 DSP VCC1V8_EN1 VCC1V8 DSP VCC1V5_EN VCC1V5 DSP DDR3 VCC0V75 DSP DDR3 FPGA_MUX_OE RESET RESETFULLz RESETSTAT PORz T 10ms T 5ms T 5...

Страница 62: ...ne Card VCC2V5 Eth PHY UCD9222_ENA1 CVDD1 DSP UCD9222_ENA2 VCC1V0 DSP VCC1V8_EN1 VCC1V8 DSP VCC1V5_EN VCC1V5 DSP DDR3 VCC0V75 DSP DDR3 FPGA_MUX_OE RESET RESETFULLz RESETSTAT PORz REF_CLKP N CLOCK2_PLL...

Страница 63: ...657 Lite EVM Reset Mechanism Control C6657 Lite EVM Clock Generator Initialization and Control TMS320C6657 DSP SPI Interface for Accessing FPGA Configurable Registers Provides Shadow Registers for TMS...

Страница 64: ...delay MMC_WR_AMC I PU MMC WARM Request This signal is used by MMC to initiate a warm reset request A logic Low to High transition on this signal will complete FPGA warm reset sequence with a specifie...

Страница 65: ...Power Down Places Clock Generator into power down state forcing the differential clock output into high impedance state UCD9222 Interface UCD9222_PG1 I UCD9222 Power Good Indication for CVDD DSP Core...

Страница 66: ...I Full Reset Button Input This button input is used to initiate a Full Reset event WARM_RESET I Warm Reset Button Input This button input is used to initiate a Warm Reset event COLD_RESET RFU I Cold...

Страница 67: ...C input DSP_TSIP1_FS A B 1 DSP TSIP1_FS A B 1 The single ended clock DSP_TSIP1_FSA1 and DSP_TSIP1_FSB1 outputs are derived from the differential TDM Frame Synchronization TDM_CLKC input DSP_TSIP0_CLK...

Страница 68: ...otect function PCIESSEN I PCIe Subsystem Enable Used for PCIESSEN switch input USER_DEFINE I User Defined Switch Reserved for user defined switch input MUX_SEL O PCIe Clock Multiplexor Input selection...

Страница 69: ..._PG asserted wait for 5ms and check the clock generator PLL_LOCK states and FPGA asserts clock MUX OE pin after the PLL state of clock generator is valid the FPGA de asserts DSP_RESETz and DSP_LRESETz...

Страница 70: ...5ms CLOCK2_PLL_LOCK T 5ms All 0 Boot Config Switches value driven by FPGA Floating by FPGA DSP GPIOs T 3 4 48MHz clock cycle Figure 5 1 Power On Reset Boot Configuration Timing RESETFULLzSW RESETFULLz...

Страница 71: ...This causes RESETSTAT to go low which triggers the boot configuration to be driven from the FPGA Reset to the Marvell PHY is also asserted POR and RESET to the DSP remain high The power supplies and c...

Страница 72: ...set o PCIe MMRs The contents of the memory connected to the EMIFA are retained The EMIFA registers are not reset COLD_RESET RST_COLD1 Not used in current implementation MMC_POR_IN_AMC A logic low stat...

Страница 73: ...TMDXEVM6657LE Page 73 90 Figure 5 3 SPI access from TMS320C6657 to FPGA WRITE high level Figure 5 4 SPI access from TMS320C6657 to FPGA WRITE The below figures illustrate a DSP to FPGA SPI read opera...

Страница 74: ...interface protocol is compatible to CDCE62005 SPI The FPGA SPI bus clocks data in on the rising edge of DSP SPI Clock Data transitions therefore occur on the falling edge of the clock The figure belo...

Страница 75: ...5 6 1 FPGA Configuration Registers Summary Table 5 4 FPGA Configuration Registers Summary Address Offset Definition Attribute R W RO Read Only Default Value 00h FPGA Device ID Low Byte RO 04h 01h FPGA...

Страница 76: ...Read Only Bit Description Read Write 7 0 FPGA Device ID Low Byte This offset 01h field combined with this field identifies the particular device This identifier is allocated by the FPGA design team RO...

Страница 77: ...Technical Reference Manual TMDXEVM6657L SPRUHG7 Revised August 2012 TMDXEVM6657LE Page 77 90...

Страница 78: ...M general purpose input signal GPIO 01 and writes will have no effect 0 BM GPIO 01 state is low 1 BM GPIO 01 state is high RO 2 BM GPIO 02 This bit reflects the state of the BM general purpose input s...

Страница 79: ...the BM general purpose input signal GPIO 10 and writes will have no effect 0 BM GPIO 10 state is low 1 BM GPIO 10 state is high RO 3 BM GPIO 11 This bit reflects the state of the BM general purpose in...

Страница 80: ...e is low 1 DSP GPIO 02 state is high RO 3 DSP GPIO 03 This bit reflects the state of the DSP general purpose input signal GPIO 03 and writes will have no effect 0 DSP GPIO 03 state is low 1 DSP GPIO 0...

Страница 81: ...ate is low 1 DSP GPIO 10 state is high RO 3 DSP GPIO 11 This bit reflects the state of the DSP general purpose input signal GPIO 11 and writes will have no effect 0 DSP GPIO 11 state is low 1 DSP GPIO...

Страница 82: ...0 DEBUG_LED 4 drives low and set the LED 4 to ON 1 DEBUG_LED 4 drives high and set the LED 4 to OFF R W 7 4 Reserved R W Register Address SPI Base 09h Register Name MMC Control Register Default Value...

Страница 83: ...tton Status Register Default Value Attribute Read Only Bit Description Read Write 0 FULL_RESET Button Status This bit reflects the FULL_RESET button state This button is used to request a power full r...

Страница 84: ...AMC_EN pin and for selection of TCLK for McBSP 00 Drive McBSP_AMC_EN low Connect TCLKA to McBSP SLCLKs TxCLKs RxCLKs Connect TCLKC to McBSP FSTs FSRs 01 Drive McBSP_AMC_EN low Connect TCLKB to McBSP S...

Страница 85: ...IO 15 is mapped to FPGA_FW_SPI_MISO RO 1 2 DSP_HOUT Status This bit reflects the DSP_HOUT signal state 0 DSP_HOUT state is low 1 DSP_HOUT state is high RO 3 DSP_SYSCLKOUT Status This bit reflects the...

Страница 86: ...bus for the CDCE62005 Clock Generator 2 is idle 1 The SPI bus for the CDCE62005 Clock Generator 2 is busy and a SPI command is processing RO 7 2 Reserved RO Register Address SPI Base 11h Register Name...

Страница 87: ...ister Address SPI Base 16h Register Name CLK GEN 2 Command Byte 2 Register Default Value 00h Attribute Read Write Bit Description Read Write 7 0 This register specifies the update SPI command byte 2 t...

Страница 88: ...eflects the read back data byte 0 from the CDCE62005 Clock Generator 2 for responding a host SPI Read Command 7 0 The SPI read back data bit 23 to bit 16 for a SPI Read Command RO Register Address SPI...

Страница 89: ...rol Register Default Value 00h Attribute Read Write Bit Description Read Write 7 0 CLK_MUX_SEL This bit can be updated by the DSP software to drive a high or low value on the CLK_MUX_SEL pin The defau...

Страница 90: ...t or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as lif...

Страница 91: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments TMDXEVM6657L...

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