Texas Instruments DS90Ux941AS-Q1EVM, Руководство пользователя

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Demo Board Connections
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8 SNLU241A – December 2018 – Revised April 2019
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DS90Ux941AS-Q1EVM User's Guide
Table 9. SPI/D_GPIO Interface
DESIGNATOR SIGNAL DESCRIPTION
J12.26 D_GPIO0/MOSI I/O in FPD-Link III mode / Master
Out, Slave In
J12.28 D_GPIO1/MISO I/O in FPD-Link III mode / Master
In, Slave Out
J12.30 D_GPIO2/SPLK I/O in FPD-Link III mode / Serial
Clock
J12.32 D_GPIO3/SS I/O in FPD-Link III mode / Slave
Select
Configuration of the device may be done through the MODE_SEL[1:0]. These modes are latched into
register location during power-up:
Table 10. MODE_SEL[1:0] Settings
MODE SETTING FUNCTION
Split
0 Disable
1 Enable
DSI Lanes
00 1 DSI Lane
01 2 DSI Lanes
10 3 DSI Lanes
11 4 DSI Lanes
Non-continuous Clock Mode
0 Continuous mode
1 Non-continuous mode
COAX
0 Enable FPD-Link III for twisted pair cabling
1 Enable FPD-Link III for coaxial cabling
Disable DSI
0 Enable DSI
1 Disable DSI
(1)
Only set one high
Table 11. Configuration Select (MODE_SEL0) - SW-DIP8 - S2
(1)
MODE
NO.
V
TARGET
VOLTAGE RANGE
V
TARGET
STRAP
VOLTAGE
SUGGESTED STRAP
RESISTORS (1% TOL)
SPLIT DSI LANES
V
MIN
V
TYP
V
MAX
(V); V
(VDD18)
=
1.8 V
R
3
(k Ω ) R
4
(k Ω )
0 0 0 0.126 ×
V
(VDD18)
0 OPEN 10.0 0 1
1 0.179 ×
V
(VDD18)
0.211 ×
V
(VDD18)
0.244 ×
V
(VDD18)
0.380 73.2 20.0 0 2
2 0.272 ×
V
(VDD18)
0.325 ×
V
(VDD18)
0.364 ×
V
(VDD18)
0.585 60.4 30.1 0 3
3 0.404 ×
V
(VDD18)
0.441 ×
V
(VDD18)
0.472 ×
V
(VDD18)
0.794 51.1 40.2 0 4
4 0.526 ×
V
(VDD18)
0.556 ×
V
(VDD18)
0.590 ×
V
(VDD18)
1.001 40.2 51.1 1 1
5 0.643 ×
V
(VDD18)
0.673 ×
V
(VDD18)
0.708 ×
V
(VDD18)
1.211 30.1 61.9 1 2
6 0.763 ×
V
(VDD18)
0.790 ×
V
(VDD18)
0.825 ×
V
(VDD18)
1.421 18.7 71.5 1 3
7 0.880 ×
V
(VDD18)
V
(VDD18)
V
(VDD18)
1.8 10 OPEN 1 4