DS90Ux941AS
FPD- Link III
Deserializer
Video
Processor
Video Processor Board
Cluster, Head Unit
Dual FPD- LINK III
Display
( Video Data + Ctrl + PCLK)
(I2C)
(I2C)
( OpenLDI)
FPD-Link III
IDx
DOUT0+
DOUT0-
DOUT1+
DOUT1-
RIN0+
RIN0-
RIN1+
RIN1-
CLK0+/-
CLK1+/-
FPD-Link
(Open LDI)
D0+/-
D1+/-
D2+/-
D3+/-
D4+/-
D5+/-
D6+/-
D7+/-
DS90Ux941AS
Serializer
DS90Ux948
Deserializer
IDx
HS_GPIO
(SPI)
HS_GPIO
(SPI)
LVDS
Display
or Graphic
Processor
Processor
I2C
I2C
CLK+/-
D0+/-
D1+/-
D2+/-
D3+/-
DSI
System Requirements
4
SNLU241A – December 2018 – Revised April 2019
Copyright © 2018–2019, Texas Instruments Incorporated
DS90Ux941AS-Q1EVM User's Guide
3
System Requirements
To demonstrate, the following is required:
1. FPD-Link III compatible Deserializer
1. DS90Ux940-Q1, DS90Ux948-Q1 up to 1080p60
2. DSI source
3. Optional I
2
C controller
4. Power supply for 12 V at 1 A (required)
4
Contents of the Demo Evaluation Kit
One EVM board with the DS90Ux941A-Q1
5
Applications Diagram
Figure 1. Applications Diagram
6
Typical Configuration
Figure 2. Typical Configuration
and
show the use of the chipset in a display application.