DOUT0_P
DOUT0_N
DOUT1_P
DOUT1_N
PDB
D_GPIO0/MOSI
D_GPIO1/MISO
D_GPIO2/SPLK
D_GPIO3/SS
INTB
SDA
SCL
GPIO1/I2C(SCL)
GPIO0/I2C(SDA)
GPIO2/SPI(SCLK)
GPIO6/PWM1/SPI(CS)
GPIO4/SPI(SIMO)/UART(TXD)
GPIO5/SPI(SOMI)/UART(RXD)
PDB_CTRL
INTB_CTRL
GND
SDA
SCL
VDDIO
GND
GND
I2S_CLK/GPIO8_REG
I2S_WC/GPIO7_REG
I2S_DA/GPIO6_REG
I2S_DB/GPIO5_REG
I2S_DC/GPIO2
I2S_DD/GPIO3
SDIN/GPIO0
SWC/GPIO1
SCLK
MCLK
D_GPIO0/MOSI
D_GPIO1/MISO
D_GPIO2/SPLK
D_GPIO3/SS
INTB
GND
DAOUT
BCK
LRCK
SCKIN
DOUT1_N
DOUT1_P
DOUT0_N
DOUT0_P
GND
SMAD0_N
SMAD0_P
SMAD1_N
SMAD1_P
GND
REM_INTB
Ground
VDDIO
GND
DSI1_D3_P
DSI1_D3_N
DSI1_D2_P
DSI1_D2_N
DSI0_D3_P
DSI0_D3_N
DSI0_D2_P
DSI0_D2_N
DSI0_CLK_P
DSI0_CLK_N
DSI0_D1_P
DSI0_D1_N
DSI0_D0_P
DSI0_D0_N
DSI1_CLK_P
DSI1_CLK_N
DSI1_D1_P
DSI1_D1_N
DSI1_D0_P
DSI1_D0_N
DSI
SCL
SDA
SDA
SCL
PDB
DSI0_CLK_N
DSI0_CLK_P
DSI0_D0_N
DSI0_D0_P
DSI0_D1_N
DSI0_D1_P
DSI0_D2_N
DSI0_D2_P
DSI0_D3_N
DSI0_D3_P
DSI1_CLK_N
DSI1_CLK_P
DSI1_D0_N
DSI1_D0_P
DSI1_D2_N
DSI1_D2_P
DSI1_D3_N
DSI1_D3_P
DSI1_D1_N
DSI1_D1_P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
19
21
23
25
27
29
31
16
18
20
22
24
26
28
30
32
J12
J9
1
3
2
4
5
7
6
8
9
11
10
12
13
15
14
16
17
19
18
20
21
23
22
24
25
27
26
28
29
31
30
32
33
35
34
36
37
39
38
40
MP1
MP2
MP3
MP4
J8
J10
2
1
4
3
PAIR A1
PAIR A2
P1
D4S20F-40MA5-Z
PDB
SDA
4
1
2
3
J11
4
1
2
3
J13
0
R73
0
R76
0
R72
0
R77
0
R79
0
R78
0
R70
0
R71
4.7k
R69
4.7k
R68
0
R74
0
R75
1
2
3
4
L4
1
2
3
4
L3
SCL
NT1
NT2
NT3
NT4
16V
0.1uF
C19
50V
4.7pF
C20
50V
4.7pF
C21
Appendix A
32
SNLU241A – December 2018 – Revised April 2019
Copyright © 2018–2019, Texas Instruments Incorporated
EVM PCB Schematics
Figure 26. Schematic Connectors