Texas Instruments CC3235MODSF SimpleLink, Руководство пользователя

Страница: 58 / 106

T2 T3 T4
T7 T8
T7 T8
T9 T10 T9 T10
T1
T11
TDI Input Valid
TDO Output Valid
TDO Output Valid
TMS Input Valid
TDI Input Valid
TCK
TMS
TDI
TDO
TMS Input Valid
58
CC3235MODS, CC3235MODSF
SWRS224A – FEBRUARY 2019 – REVISED AUGUST 2019 www.ti.com
Submit Documentation Feedback
Product Folder Links: CC3235MODS CC3235MODSF
Specifications
Copyright © 2019, Texas Instruments Incorporated
5.18.5.5 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and
boundary scan architecture for digital integrated circuits and provides a standardized serial interface to
control the associated test logic. For detailed information on the operation of the JTAG port and TAP
controller, see the IEEE Standard 1149.1,
Test Access Port and Boundary-Scan Architecture .
Figure 5-14 shows the JTAG timing diagram.
Figure 5-14. JTAG Timing Diagram
Table 5-21 lists the JTAG timing parameters.
Table 5-21. JTAG Timing Parameters
ITEM NAME DESCRIPTION MIN MAX UNIT
T1 f
TCK
Clock frequency 15 MHz
T2 t
TCK
Clock period 1 / f
TCK
ns
T3 t
CL
Clock low period t
TCK
/ 2 ns
T4 t
CH
Clock high period t
TCK
/ 2 ns
T7 t
TMS_SU
TMS setup time 1 ns
T8 t
TMS_HO
TMS hold time 16 ns
T9 t
TDI_SU
TDI setup time 1 ns
T10 t
TDI_HO
TDI hold time 16 ns
T11 t
TDO_HO
TDO hold time 15 ns