Texas Instruments CC112 Series Скачать руководство пользователя страница 52 | Manualshive

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Texas Instruments CC112 Series Скачать руководство пользователя страница 52

CC112X/CC1175

SWRU295C

Page 52 of 108

7.7.2

Transparent Serial Mode

CC112X

does not do any timing recovery and just outputs the hard limited baseband signal. In

transparent  serial  mode  the  data  rate  programming  does  not  affect  operation.  When  transparent
mode  is  enabled,  the  device  is  set  up  to  resemble  a  legacy  purely  analog  front  end  device  with
baseband  output  to  support  legacy  pulse  position  modulation,  PWM  modulated  signals  etc.  In
transparent  mode  the  signal  is  digitally  demodulated  and  output  on  GPIO  pins  through  a
programmable interpolation filter (

MDMCFG0.TRANSPARENT_INTFACT

). The interpolation filter is used

to eliminate jitter on the baseband signal. This is useful when using external DSP demodulators as
jitter introduce noise in the demodulation process. The rate on the GPIO is ((4 x receiver bandwidth) x
interpolation factor).

When using transparent serial mode make sure the interfacing MCU/DSP does proper oversampling.
In transparent serial mode, several of the support mechanisms for the MCU that are included in

CC112X

will be disabled, such as packet handling hardware, buffering in the FIFO, and so on.

Preamble and sync word insertion/detection is not supported in transparent serial mode.

For TX operation, the GPIO0 pin is explicitly used as serial data input. This is automatically done
when in TX. In order to avoid internal I/O conflict, GPIO0 should be defined as tri-state. GPIO0 will be
automatically tri-stated in TX if the GPIO0 is defined as serial clock or serial data output
(

IOCFG0.GPIO0_CFG = 8

or

9

). If this is not the case, GPIO0 must be manually tri-stated by

setting

IOCFG0.GPIO0_CFG = HIGHZ

(48).

Data output can be observed on GPIO0/1/2/3. This is set by the

IOCFGx.GPIOx_CFG

fields.

In addition to set

PKT_CFG2.PKT_FORMAT = 11b

, the following register fields must be set:

MDMCFG1.FIFO_EN = 0

MDMCFG0.TRANSPARENT_MODE_EN = 1

IOCFGx.GPIOx_CFG = 001001b

. Only necessary for RX mode)

SERIAL_STATUS.IOC_SYNC_PINS_EN = 1

(Only necessary for TX mode)

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Содержание CC112 Series

Страница 1: ...CC112X CC1175 SWRU295C Page 1 of 108 CC112X CC1175 Low Power High Performance Sub 1 GHz RF Transceivers Transmitter User s Guide...

Страница 2: ...eck PLL Phase Locked Loop CS Carrier Sense POR Power On Reset DC Direct Current PQT Preamble Quality Threshold ESR Equivalent Series Resistance QPSK Quadrature Phase Shift Keying FCC Federal Communica...

Страница 3: ...NFIGURATION 41 6 1 PA OUTPUT POWER PROGRAMMING 41 6 2 OOK ASK BIT SHAPING 41 7 PACKET HANDLING HARDWARE SUPPORT 42 7 1 STANDARD PACKET FORMAT 42 7 2 PACKET FILTERING IN RECEIVE MODE 48 7 3 PACKET HAND...

Страница 4: ...9 4 CONTINUOUS TRANSMISSIONS 67 9 5 BATTERY OPERATED SYSTEMS 67 10 REGISTER DESCRIPTION 68 11 SOLDERING INFORMATION 106 12 DEVELOPMENT KIT ORDERING INFORMATION 106 13 REFERENCES 107 14 GENERAL INFORM...

Страница 5: ...data output for legacy protocols Data interface with signal chain access XOSC_Q1 XOSC_Q2 Ultra low power 32 40 kHz auto calibrated RC oscillator Optional 32kHz clock intput CSn Chip Select SI Serial I...

Страница 6: ...hesizer is turned on can optionally be calibrated and then settles to the correct frequency Transitional state Frequency synthesizer is on ready to start transmitting Transmission starts very quickly...

Страница 7: ...done most significant bit first All transactions on the SPI interface start with a header byte containing a R W bit a burst access bit B and a 6 bit address A5 A0 A status byte is sent on the SO pin...

Страница 8: ...n be accessed in an efficient way by setting the burst bit B in the header byte The address bits A5 A0 set the start address in an internal address counter This counter is incremented by one each new...

Страница 9: ..._END Transmit mode 011 FSTXON FSTXON Fast TX ready 100 CALIBRATE BIAS_SETTLE_MC REG_SETTLE_MC MANCAL STARTCAL ENDCAL Frequency synthesizer calibration is running 101 SETTLING BIAS_SETTLE REG_SETTLE BW...

Страница 10: ...e following the address byte Consecutive bytes are expected after the address byte and the burst access is terminated by setting CSn high The chip status byte is returned on the SO line both when the...

Страница 11: ...he crystal oscillator entering TX etc No data byte is expected The chip status byte is returned on the SO line when a command strobe is sent on the SI line Direct FIFO Access Command R W B 1 1 1 1 1 0...

Страница 12: ..._CS_THR 0x19 AGC_GAIN_ADJUST 0x1A AGC_CFG3 0x1B AGC_CFG2 0x1C AGC_CFG1 0x1D AGC_CFG0 0x1E FIFO_CFG 0x1F DEV_ADDR 0x20 SETTLING_CFG 0x21 FS_CFG 0x22 WOR_CFG1 0x23 WOR_CFG0 0x24 WOR_EVENT0_MSB 0x25 WOR_...

Страница 13: ...FSET Yes 0x0A FREQOFF1 Yes 0x0B FREQOFF0 Yes 0x0C FREQ2 Yes 0x0D FREQ1 Yes 0x0E FREQ0 Yes 0x0F IF_ADC2 Yes 0x10 IF_ADC1 Yes 0x11 IF_ADC0 Yes 0x12 FS_DIG1 Yes 0x13 FS_DIG0 Yes 0x14 FS_CAL3 Yes 0x15 FS_...

Страница 14: ...RF_TEST No 0x98 PRE_TEST No 0x99 PRE_OVR No 0x9A ADC_TEST No 0x9B DVC_TEST No 0x9C ATEST No 0x9D ATEST_LVDS No 0x9E ATEST_MODE No 0x9F XOSC_TEST1 No 0xA0 XOSC_TEST0 No 0xA1 0xD1 Not Used 0xD2 RXFIRST...

Страница 15: ...h the RX FIFO Only issue SFRX in IDLE or RX_FIFO_ERR states 0x3B SFTX Flush the TX FIFO Only issue SFTX in IDLE or TX_FIFO_ERR states 0x3C SWORRST Reset the eWOR timer to the Event1 value 0x3D SNOP No...

Страница 16: ...D0 transmitted on the air STX transmitted on the air 2 D1 D2 0 1 2 3 4 5 6 7 8 9 10 126 127 1 D0 2 3 x x D1 D2 D3 D4 D5 x x TXFIRST TXLAST NUM_TXBYTES 0x04 STX transmitted on the air 3 D3 D4 D5 0 1 2...

Страница 17: ...s would end up with the values shown in Figure 8 0 1 2 3 4 5 6 7 8 9 10 126 127 x x RXFIRST RXLAST x x x x D0 D1 D2 NUM_RXBYTES 0x04 D0 D1 D2 x Figure 8 FIFO Pointers RX FIFO 2 3 2 4 Standard FIFO Acc...

Страница 18: ...unctionality All pin control command strobes are executed immediately except the SPWD strobe The SPWD strobe is delayed until CSn goes high Pin control is useful to get precise timing on RX TX strobes...

Страница 19: ...eshold 3 TXFIFO_THR_PKT Associated to the TX FIFO Asserted when the TX FIFO is full De asserted when the TX FIFO is drained below 127 FIFO_CFG FIFO_THR 4 RXFIFO_OVERFLOW Asserted when the RX FIFO has...

Страница 20: ...n 4 1 6 for more details 19 PKT_CRC_OK Asserted in RX when PKT_CFG1 CRC_CFG 01b or 10b and a good packet is received This signal is always on if the radio is in TX or if the radio is in RX and PKT_CFG...

Страница 21: ...w CORDIC magnitude sample 2 CHFILT_VALID New channel filter sample 1 RCC_CAL_VALID RCOSC calibration has been performed at least once 0 CHFILT_STARTUP_VALID Channel filter has settled 41 3 COLLISION_F...

Страница 22: ...rnal oscillator enable used to control e g a TCXO Note that this signal is only asserted is a TCXO is present 61 63 Reserved used for test Table 10 GPIO Output Pin Mapping 3 4 1 2 MARC MCU Wake Up The...

Страница 23: ...RX mode and when RFEND_CFG0 TERM_ON_BAD_PKT is enabled Note In eWOR Normal Feedback modes the wake up pulse will not be asserted and the CC112X will go to SLEEP until the next time slot 00000111 TX F...

Страница 24: ...ture improves adjacent channel power ACP and occupied bandwidth When selecting 4 G FSK the preamble and sync word is sent using 2 G FSK see Figure 9 1 1 3 1 3 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 00 01 0...

Страница 25: ...3 Deviation Deviation 3 Deviation 11 Deviation Deviation 3 Deviation Deviation 3 Table 12 Symbol Encoding for 2 G FSK and 4 G FSK Modulation 4 1 2 Amplitude Modulation ASK and on off keying OOK CC112...

Страница 26: ...olution PLL and lets the user in a simple way directly control read the instantaneous frequency without SPI overhead Custom frequency modulation is enabled by setting SOFT_TX_DATA_CFG SOFT_TX_DATA_EN...

Страница 27: ...effective data rate in kbps is reduced by 4 compared to the programmed data rate in ksps The PN gold sequence is generated from a combination of two 7 bits LFSR registers with generator polynomial giv...

Страница 28: ...erial mode must be selected PKT_CFG2 PKT_FORMAT 01b MDMCFG1 FIFO_EN 0 and MDMCFG0 TRANSPARENT_MODE_EN 0 It is the MCU s responsibility to extract the demodulated data which are available on GPIO by co...

Страница 29: ...TA f R M DATARATE Equation 9 DATARATE_M If DATARATE_M is rounded to the nearest integer and becomes 2 20 one should increment DATARATE_E and use DATARATE_M 0 instead The data rate can be set up to 100...

Страница 30: ...figurations supported by the CC112X ADC_CIC_DECFACT 0 ADC_CIC_DECFACT 1 BB_CIC_DECFACT RX Filter BW kHz BB_CIC_DECFACT RX Filter BW kHz 0x01 250 0x01 156 0x03 83 0x02 78 0x05 50 0x03 52 0x0A 25 0x06 2...

Страница 31: ...DE o Sets the correct gain tables to be applied for a given operation mode See Table 18 See the complete register description for what the different modes are 39 dB Index 0 27 dB Index 0 36 dB Index 1...

Страница 32: ...sampling frequency which is 4 times the programmed RX filter BW AGC_CFG1 AGC_SETTLE_WAIT o Sets the wait time between AGC gain adjustments AGC_CFG2 AGC_MAX_GAIN o Sets the maximum gain AGC_CFG3 AGC_MI...

Страница 33: ...serted at the start of the packet by the modulator The MSB in the sync word is sent first In RX mode the demodulator uses the sync word to find the start of the incoming packet The CC112X will continu...

Страница 34: ...n be monitored on a GPIO pin by setting IOCFGx GPIOx_CFG PQT_VALID 12 5 8 RSSI The AGC module returns an estimate on the signal strength received at the antenna called RSSI Received Signal Strength In...

Страница 35: ...s when CS is updated with respect to the RSSI Signal Strength Time RSSI Update CS Threshold RSSI CARRIER_SENSE Figure 13 CS vs RSSI_UPDATE Figure 14 shows an example of the behavior of RSSI specific s...

Страница 36: ...CNT 00b the number of new input samples to the moving average filter is 2 making the CS response time short but might lead to a less robust CS indication on the second RSSI update In the case where AG...

Страница 37: ...f DECFACT CIC BB 2 Factor Decimation 2 _ _ Table 21 D0 D6 ion Configurat Current 0 Delays Applicable T Equation 15 T0 The maximum carrier sense response time is given by Equation 16 1 2 2 1 0 Time Re...

Страница 38: ...eceived 5 8 1 Carrier Sense CS Carrier Sense CS is asserted when the RSSI is above a programmable CS threshold AGC_CS_THR and de asserted when RSSI is below the same threshold The CS threshold should...

Страница 39: ...a 010101 preamble sequence a check for a step in RSSI should also be done before running the SRX strobe command Also in this case one should read the NUM_RXBYTES register before strobing SRX over agai...

Страница 40: ...stening time tF shall be 5 ms b The pseudo random listening time tPS shall be randomly varied between 0 ms and a value of 5 ms or more in equal steps of approximately 0 5 ms as the following If the ch...

Страница 41: ...P The intermediate power levels and total ramp time can be configured For the shaped ramp up the output power level is split into 16 sections see where 1 equals the output power level The two intermed...

Страница 42: ...and CRC status can be appended in the RX FIFO by setting PKT_CFG1 APPEND_STATUS 1 Bit Field Name Description 7 0 RSSI RSSI value Table 22 Received Packet Status Byte 1 first byte appended after the da...

Страница 43: ...med through PKT_CFG0 PKT_BIT_LEN If m 0 only m bits of the last byte written to the TX FIFO is transmitted and RX mode is terminated when the last m bits of the packet is received This is very useful...

Страница 44: ...e MCU reads out enough bytes to interpret the length field in the packet and sets the PKT_LEN register to mod length 256 13 When less than 256 bytes remains of the packet the MCU disables infinite pac...

Страница 45: ...eing transmitted This is shown in Figure 18 At the receiver end the data are XORed with the same pseudo random sequence In this way the whitening is reversed and the original data appear in the receiv...

Страница 46: ...0 0x9A 0x9A The complete packet will look like this assume default preamble sync word and CRC configuration 0xAA 0xAA 0xAA 0xAA 0x93 0x0B 0x51 0xDE 0x54 0x61 0xE2 0x9A 0xF9 0x9D 7 1 7 Data Byte Swap I...

Страница 47: ...acket engine inserts and removes start stop bits automatically In this mode the packet engine will emulate UART back to back transmissions typically done over an asynchronous RF interface to enable co...

Страница 48: ...N_BAD_PACKET_EN setting the RFEND_CFG1 RXOFF_MODE setting is ignored 7 2 3 CRC Filtering The filtering of a packet when CRC check fails is enabled by setting FIFO_CFG CRC_AUTOFLUSH 1 The CRC auto flus...

Страница 49: ...exit this state is by issuing an SFTX strobe Writing to the TX FIFO after it has underflowed will not restart TX mode If whitening is enabled everything following the sync words will be whitened Whit...

Страница 50: ...YTES registers The IOCFGx GPIOx_CFG RXFIFO_THR 0 and the IOCFGx GPIOx_CFG RXFIFO_THR_PKT 1 configurations are associated with the RX FIFO while the IOCFGx GPIOx_CFG TXFIFO_THR 2 and the IOCFGx GPIOx_C...

Страница 51: ...s automatically done when in TX In order to avoid internal I O conflict GPIO0 should be defined as tri state GPIO0 will be automatically tri stated in TX if the GPIO0 is defined as serial clock or ser...

Страница 52: ...sure the interfacing MCU DSP does proper oversampling In transparent serial mode several of the support mechanisms for the MCU that are included in CC112X will be disabled such as packet handling hard...

Страница 53: ...possibilities on the CC112X are issuing using the SRES command strobe or using the RESET_N pin By issuing a manual reset all internal registers are set to their default values and the radio will enter...

Страница 54: ...eceived the radio controller goes to the state indicated by the RFEND_CFG1 RXOFF_MODE setting i e IDLE FSTXON TX or RX When a bad packet is received packet length address CRC error the radio controlle...

Страница 55: ...ller will check the condition for staying in RX The programmable conditions are RFEND_CFG1 RX_TIME_QUAL 0 Continue receive if sync word has been found RFEND_CFG1 RX_TIME_QUAL 1 Continue receive if syn...

Страница 56: ...ger true As shown in the figure the radio remains in RX after the 10 ms timeout even if a preamble is no longer present PQT_REACHED will be de asserted as it only checks the condition for staying in R...

Страница 57: ...4 RX_TIME_QUAL 0 RFEND_CFG0 ANT_DIV_RX_TERM_CFG 001b CARRIER_SENSE IDLE 15 16 Time ms RX 1 2 3 4 5 IDLE 14 RX_TIME_QUAL 1 RFEND_CFG0 ANT_DIV_RX_TERM_CFG 001b CARRIER_SENSE IDLE 15 16 Time ms RX termin...

Страница 58: ...R_TIME0 Every time a sync word is found the current value of the eWOR timer will be captured and it can be read through the WOR_CAPTURE1 and WOR_CAPTURE0 registers This feature is useful in applicatio...

Страница 59: ...ill be issued as soon as CHIP_RDYn is asserted Event 2 can used to autonomously take the system out of SLEEP at regular intervals to perform RC oscillator calibration This will improve the accuracy of...

Страница 60: ...back to SLEEP automatically If a good packet is being received the radio enters the state indicated by the RFEND_CFG1 RXOFF_MODE setting and when a bad packet is received it will either restart RX or...

Страница 61: ...Mode RX and TX re synchronized 8 7 RX Sniff Mode For battery operated systems the RX current is an important parameter and to increase battery lifetime a novel RX Sniff Mode feature has been designed...

Страница 62: ...ceiver can implement RX Sniff Mode and wake up at an interval that ensures that at least 4 bits of preamble is received RX termination based on CS greatly reduces the time in RX and forces the radio b...

Страница 63: ...e over a long period of time will cause internal heating of the chip which again might cause the RC OSC period to increase It is therefore recommended to turn off RCOSC calibration during active mode...

Страница 64: ...only be updated when the radio is in the IDLE state 8 12 RF Programming RF programming in CC112X is given by two factors the VCO frequency programming and the LO divider programming RF band selection...

Страница 65: ...or an overview of the RF resolution RF Programming Resolution Hz RF Band MHz XOSC 32 MHz XOSC 40 MHz 820 960 30 5 38 1 410 480 15 3 19 1 273 3 320 10 2 12 7 205 240 7 6 9 5 164 192 6 1 7 6 136 7 160 5...

Страница 66: ...0 In order to meet EN 300 220 2 Category 1 adjacent channel selectivity requirements FS_CHP CHP_CAL_CURR must be altered after calibration as shown in Figure 32 Figure 32 CC1125 Category 1 8 15 FS Out...

Страница 67: ...ity makes the system more robust with respect to interference from other systems operating in the same frequency band FHSS also combats multipath fading CC112X is highly suited for FHSS or multi chann...

Страница 68: ...Transfer Enable Refer to IOCFG3 6 GPIO1_INV 0x00 R W Invert Output Enable Refer to IOCFG3 5 0 GPIO1_CFG 0x30 R W Output Selection Default HIGHZ Note that GPIO1 is shared with the SPI and act as SO whe...

Страница 69: ...gth Configuration When SYNC_MODE 000b all samples noise or data received after RX mode is entered will either be put in the RX FIFO or output on a GPIO configured as SERIAL_RX Note that when 4 ary mod...

Страница 70: ...CC1120 CC1121 and CC1175 this setting is reserved 2 0 DEV_E 0x03 R W Frequency Deviation exponent part DEV_E 0 E DEV xosc dev M DEV f f _ 24 2 _ 256 2 DEV_E 0 M DEV f f xosc dev _ 223 DCFILT_CFG Digi...

Страница 71: ...Configuration Bit no Name Reset R W Description 7 6 PREAMBLE_CFG0_NOT_USED 0x00 R 5 PQT_EN 0x01 R W Preamble Detection Enable 0 Preamble detection disabled 1 Preamble detection enabled 4 PQT_VALID_TIM...

Страница 72: ...Q0 registers are updated 5 4 IQIC_BLEN_SETTLE 0x00 R W IQIC Block Length when Settling The IQIC module will do a coarse estimation of IQ imbalance coefficients during settling mode Long block length i...

Страница 73: ...d bypassed 2 _ _ Factor Decimation BW Filter RX DECFACT CIC BB fXOSC Decimation factor given by ADC_CIC_DECFACT 6 ADC_CIC_DECFACT 0x00 R W ADC_CIC_DECFACT is a table index which programs the first dec...

Страница 74: ...0 NRZ 1 Manchester encoding decoding 4 INVERT_DATA_EN 0x00 R W Invert Data Enable Invert payload data stream in RX and TX only applicable to payload data including optional CRC 0 Invert data disabled...

Страница 75: ...d extended data filter disabled 01 Transparent data filter disabled and extended data filter enabled 10 Transparent data filter disabled and extended data filter disabled 11 Transparent data filter en...

Страница 76: ...is needed AGC_CS_THR Carrier Sense Threshold Configuration Bit no Name Reset R W Description 7 0 AGC_CS_THRESHOLD 0x00 R W AGC Carrier Sense Threshold Two s complement number with 1 dB resolution AGC_...

Страница 77: ...eset R W Description 7 5 AGC_SYNC_BEHAVIOR 0x05 R W AGC behavior after sync word detection 000 No AGC gain freeze Keep computing updating RSSI 001 AGC gain freeze Keep computing updating RSSI 010 No A...

Страница 78: ...GC Slew Rate Limit Limits the maximum front end gain adjustment 00 60 dB 01 30 dB 10 18 dB 11 9 dB 3 2 RSSI_VALID_CNT 0x00 R W Gives the number of new input samples to the moving average filter intern...

Страница 79: ...ds are reached DEV_ADDR Device Address Configuration Bit no Name Reset R W Description 7 0 DEVICE_ADDR 0x00 R W Address used for packet filtering in RX SETTLING_CFG Frequency Synthesizer Calibration a...

Страница 80: ...k detector enabled 3 0 FSD_BANDSELECT 0x02 R W Band Select Setting for LO Divider 0000 Not in use 0001 Not in use 0010 820 0 960 0 MHz band LO divider 4 0011 Not in use 0100 410 0 480 0 MHz band LO di...

Страница 81: ...nd XOSC RES WOR TIME RX f EVENT FLOOR MAX 1250 2 2 0 1 Timeout RX _ 4 3 _ 00 High resolution 01 Medium high resolution 10 Medium low resolution 11 Low resolution 5 3 WOR_MODE 0x01 R W eWOR Mode 000 Fe...

Страница 82: ...ed If calibration is enabled WOR_CFG0 RC_PD must be 0 00 RCOSC calibration disabled 01 RCOSC calibration disabled 10 RCOSC calibration enabled 11 RCOSC calibration is enabled on every 4th time the dev...

Страница 83: ..._EN must be set to 0 and MDMCFG0 TRANSPARENT_MODE_EN must be set to 1 This mode is only supported for 2 ary modulation formats PKT_CFG1 Packet Configuration Reg 1 Bit no Name Reset R W Description 7 P...

Страница 84: ...LEN_BIT 0 1 UART_MODE_EN 0x00 R W UART Mode Enable When enabled the packet engine will insert remove a start and stop bit to from the transmitted received bytes 0 UART mode disabled 1 UART mode enable...

Страница 85: ...CS PQT are disabled 001 RX termination based on CS is enabled Antenna diversity OFF 010 Single switch antenna diversity on CS enabled One or both antenna is CS evaluated once and RX will terminate if...

Страница 86: ..._NOT_USED 0x00 R 6 3 ASK_DEPTH 0x0F R W ASK OOK Depth 2 dB step size 18 2 1 _ _ RAMP POWER PA AMAX DEPTH ASK RAMP POWER PA AMIN _ 2 18 2 1 _ _ PA_POWER_RAMP must be 0x03 and PA_POWER_RAMP 4 ASK_DEPTH...

Страница 87: ...C in FS enabled Loop gain factor is 1 512 typical 2 4 preamble bytes for settling 2 FOC_LIMIT 0x00 R W FOC Limit This is the maximum frequency offset correction in the frequency synthesizer Only valid...

Страница 88: ...iming Error Proportional Scale Factor X00 Proportional scale factor 8 16 X01 Proportional scale factor 6 16 X10 Proportional scale factor 2 16 X11 Proportional scale factor 1 16 1XX Proportional scale...

Страница 89: ..._CLOCK_FREQ 0x00 R W External Clock Frequency Controls division factor 00000 64 00001 62 00010 60 00011 58 00100 56 00101 54 00110 52 00111 50 01000 48 01001 46 01010 44 01011 42 01100 40 01101 38 011...

Страница 90: ...iguration Bit no Name Reset R W Description 7 3 EXT_CTRL_NOT_USED 0x00 R 2 PIN_CTRL_EN 0x00 R W Pin Control Enable Pin control reuses the SPI interface pins to execute SRX STX SPWD and IDLE strobes 0...

Страница 91: ...7 0 FREQ_15_8 0x00 R W Frequency 15 8 See FREQ2 FREQ0 Frequency Configuration 7 0 Bit no Name Reset R W Description 7 0 FREQ_7_0 0x00 R W Frequency 7 0 See FREQ2 IF_ADC2 Analog to Digital Converter C...

Страница 92: ...ption 7 6 FS_CAL2_NOT_USED 0x00 R 5 0 VCDAC_START 0x20 R W VCDAC start value Use value from SmartRF Studio FS_CAL1 Bit no Name Reset R W Description 7 0 FS_CAL1_RESERVED7_0 0x00 R W For test purposes...

Страница 93: ...et R W Description 7 FSD_PFD_NOT_USED 0x00 R 6 0 FS_PFD_RESERVED6_0 0x51 R W For test purposes only use values from SmartRF Studio FS_PRE Prescaler Configuration Bit no Name Reset R W Description 7 FS...

Страница 94: ...W Description 7 6 GBIAS4_NOT_USED 0x00 R 5 0 GBIAS4_RESERVED5_0 0x00 R W For test purposes only use values from SmartRF Studio GBIAS3 Global Bias Configuration Reg 3 Bit no Name Reset R W Description...

Страница 95: ...on even if an SXOFF SPWD or SWOR command strobe has been issued This can be used to enable fast start up from SLEEP XOFF on the expense of a higher current consumption XOSC1 Crystal Oscillator Config...

Страница 96: ...T_OFFSET_I_15_8 0x00 R W DC Compensation Real Value 15 8 DCFILTOFFSET_I0 DC Filter Offset I LSB Bit no Name Reset R W Description 7 0 DCFILT_OFFSET_I_7_0 0x00 R W DC Compensation Real Value 7 0 DCFILT...

Страница 97: ...e given by RSSI 11 0 This RSSI offset value can either be subtracted from RSSI 11 0 manually or the offset can be written to AGC_GAIN_ADJUST GAIN_ADJUSTMENT meaning that RSSI 11 0 will give a correct...

Страница 98: ...11 RX 4 0 MARC_STATE 0x01 R MARC State 00000 SLEEP 00001 IDLE 00010 XOFF 00011 BIAS_SETTLE_MC 00100 REG_SETTLE_MC 00101 MANCAL 00110 BIAS_SETTLE 00111 REG_SETTLE 01000 STARTCAL 01001 BWBOOST 01010 FS...

Страница 99: ...s the radio is in RX searching for a sync word the register field will be updated continuously DEM_STATUS Demodulator Status Bit no Name Reset R W Description 7 RSSI_STEP_FOUND 0x00 R Asserted if RSSI...

Страница 100: ...ing burst mode to do custom demodulation 64 _ _ DATA RX SOFT f f DEV OFFSET two s complement format fDEV is the programmed frequency deviation SOFT_TX_DATA_IN Soft TX Data Input Register Bit no Name R...

Страница 101: ...nel filter samples 2 0 DEM_CHFILT_I_18_16 0x00 R Channel filter data real part 19 bit 18 16 CHFILT_I1 Channel Filter Data Real Part 15 8 Bit no Name Reset R W Description 7 0 DEM_CHFILT_I_15_8 0x00 R...

Страница 102: ...Serial RX data clock RX_STATUS RX Status Bit no Name Reset R W Description 7 SYNC_FOUND 0x00 R Asserted simultaneously as SYNC_EVENT De asserted when an SRX strobe has been issued 6 RXFIFO_FULL 0x00...

Страница 103: ...discarded due to maximum length filtering 00000101 Packet discarded due to address filtering 00000110 Packet discarded due to CRC filtering 00000111 TX FIFO overflow error occurred 00001000 TX FIFO un...

Страница 104: ...iption 7 4 ATEST_LVDS_NOT_USED 0x00 R 3 0 ATEST_LVDS_RESERVED3_0 0x00 R W For test purposes only use values from SmartRF Studio ATEST_MODE Bit no Name Reset R W Description 7 0 ATEST_MODE_RESERVED7_0...

Страница 105: ...e RX FIFO FIFO_NUM_TXBYTES TX FIFO Status free entries Bit no Name Reset R W Description 7 4 FIFO_NUM_TXBYTES_NOT_USED 0x00 R 3 0 FIFO_TXBYTES 0x0F R Number of free entries in the TX FIF0 1111b means...

Страница 106: ...rable Evaluation Module Description CC1120DK Performance Line Development Kit CC1120EMK 169 CC1120 Evaluation Module Kit 169 MHz CC1120EMK 420 470 Evaluation Module Kit 420 470 MHz CC1120EMK 868 915 C...

Страница 107: ...1 SmartRF Studio SWRC176 zip 2 EN 300 220 V2 3 1 Electromagnetic compatibility and Radio spectrum Matters ERM Short Range Devices SRD Radio equipment to be used in the 25 MHz to 1000 MHz frequency ra...

Страница 108: ...added to Equation 18 saying that the equation is only an approximation Added Section 8 14 1 regarding CC1125 Category 1 Operation under EN 300 220 Added info to Section 9 3 regarding which registers...

Страница 109: ...or use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have...

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