CC112X/CC1175
SWRU295C
Page 49 of 108
7.2.4
Auto Acknowledge
By configuring the radio to enter TX after a packet has been received (
TX
) enabling termination on bad packets (
RFEND_CFG0.TERM_ON_BAD_PACKET_EN = 1
) automatic
acknowledgement of packets can be achieved. The Ack. packet should be written to the TX FIFO
before RX mode is being entered. With the settings described above, receiving a bad packet (error in
address, length, or CRC) will have the radio enter IDLE state while receiving a good packet will cause
the radio to enter TX state and transmit the packet residing in the TX FIFO.
7.3
Packet Handling in Transmit Mode
The payload that is to be transmitted must be written into the TX FIFO. The first byte written must be
the length byte when variable packet length is enabled (
PKT_CFG0.LENGTH_CONFIG = 01b
). The
length byte has a value equal to the payload of the packet (including the optional address byte). If
address recognition is enabled in the receiver (
PKT_CFG1.ADDR_CHECK_CFG ≠ 00b
) the second
byte written to the TX FIFO must be the address byte (as the address in not automatically inserted).
If fixed packet length is enabled (
PKT_CFG0.LENGTH_CONFIG = 00b
), the first byte written to the
TX FIFO should be the address (assuming the receiver uses address recognition).
The modulator will first send the programmed number of preamble bytes configured through the
register
field.
If
data
is
available
in
the
TX FIFO, the modulator will send the sync word (programmed through
) followed by the payload in the TX FIFO. If CRC is enabled (
01b
or
10b
), the checksum is calculated over all the data pulled from the TX FIFO, and the result is
sent as two extra bytes following the payload data. If the TX FIFO runs empty before the complete
packet has been transmitted, the radio will enter TX_FIFO_ERR state. The only way to exit this state
is by issuing an
strobe. Writing to the TX FIFO after it has underflowed will not restart TX mode.
If whitening is enabled, everything following the sync words will be whitened. Whitening is enabled by
setting
PKT_CFG1.WHITE_DATA = 1
. For more details on whitening, please see Section 7.1.6.
7.4
Packet Handling in Receive Mode
In receive mode, the radio will search for a valid sync word (if
SYNC_CFG0.SYNC_MODE ≠ 0
) and
when found, the demodulator has obtained both bit and byte synchronization and will receive the first
payload byte. For more details on byte synchronization/sync word detection, please see Section 5.6
If whitening is enabled (
), the data will be de-whitened at this stage.
When variable packet length mode is enabled (
PKT_CFG0.LENGTH_CONFIG = 01b
), the first byte is
the length byte. The packet handler stores this value as the packet length and receives the number of
bytes indicated by the length byte. If fixed packet length mode is used (
= 00
), the packet handler will accept the number of bytes programmed through the
Next, the packet handler optionally checks the address (if
PKT_CFG1.ADDR_CHECK_CFG ≠ 00b
)
and only continues the reception if the address matches. If automatic CRC check is enabled
(
PKT_CFG1.CRC_CFG = 01b
or
10b
), the packet handler computes CRC and matches it with the
appended CRC checksum.
At the end of the payload, the packet handler will optionally write two extra packet status bytes (see
Table
and
that
contain
CRC
status,
LQI,
and
RSSI
value
if
.
7.5
Packet Handling in Firmware
When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a
packet has been received/transmitted. Additionally, for packets longer than 128 bytes, the RX FIFO
needs to be read while in RX and the TX FIFO needs to be refilled while in TX. This means that the
MCU needs to know the number of bytes that can be read from or written to the RX FIFO and TX
FIFO respectively. There are two possible solutions to get the necessary status information: