Texas Instruments BQ769142, Руководство пользователя

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Typical values stated where T
A
= 25°C and V
BAT
= 59.2 V, min/max values stated where T
A
= -40°C to 85°C and V
BAT
= 4.7 V
to 80 V (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
B
(ADC_DNL)
Differential
nonlinearity 16-bit, no missing codes, using differential
cell voltage measurement at VC14-VC13A
±0.12 LSB
(5)
B
(ADC_OFF_CELL)
Differential cell offset
error
16-bit, uncalibrated, using VC14 - VC13A –2.75 3.5 LSB
(5)
B
(ADC_OFF)
ADCIN offset error
16-bit, uncalibrated, using ADCIN mode on
TS1 pin
0.53 LSB
(6)
B
(ADC_OFF_DIV)
Divider offset error
16-bit, uncalibrated, using divider mode on
PACK pin
0.17 LSB
(8)
B
(ADC_OFF_DRIFT_CELL)
Differential cell offset
error drift
(4)
Offset error measured 16-bit, post calibration,
using VC14 - VC13A. Drift measured as
change in offset over operating temperature
range as compared to offset at 30°C.
0.004 0.07 LSB/°C
(5)
B
(ADC_GAIN)
Gain
Gain measured 16-bit, over ideal input
voltage range, differential cell input mode on
VC14-VC13A, uncalibrated.
5385 5406 5427 LSB/V
(5)
B
(ADC_GAIN_DRIFT)
Gain drift
(4)
Gain measured 16-bit, over ideal input
voltage range, differential cell input mode on
VC14-VC13A, uncalibrated. Drift value
measured as change in gain over operating
temperature range, compared to gain at
30°C.
-0.25 0.025 0.25
LSB/V/
°C
(5)
R
(ADC_IN_CELL)
Effective input
resistance
(3)
Differential cell input mode on VC14-
VC13A
(9)
2.1 MΩ
R
(ADC_IN_LD)
Effective input
resistance Divider measurement on LD pin (only active
while the LD pin is being measured)
2 MΩ
R
(ADC_IN_DIV)
Effective input
resistance
Divider measurement on VC14 and PACK
pins (only active while the pin is being
measured)
600 kΩ
B
(ADC_RES)
Code stability
(2) (4)
Single conversion, in NORMAL
mode,
Settings:Configuration:Power
Config[FASTADC] = 0
13.5 15 bits
B
(ADC_RES_FAST)
Code stability in fast
mode
(2)
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[FASTADC]
= 1
14 bits
t
(ADC_CONV)
Conversion-time
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[FASTADC]
= 0
2.93 ms
t
(ADC_CONV_FAST)
Conversion-time in
fast mode
Single conversion, in NORMAL mode,
Settings:Configuration:Power
Config[FASTADC]
= 1
1.46 ms
(1) Operation with V
BAT
up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in
5.5 V or 11 V mode), the maximum voltage on V
BAT
should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed
their maximum specified voltage.
(2) Code stability is defined as the resolution such that the data exhibits 3-sigma variation within ±1-LSB.
(3) Specified by design
(4) Specified by characterization
(5) The 16-bit LSB size of the differential cell voltage measurement is given by 1 LSB = 5 x V
REF1
/ 2
N-1
≈ 5 x 1.215 V / 2
15
= 185 µV
(6) The 16-bit LSB size of the ADCIN voltage measurement is given by 1 LSB = 5 / 3 x V
REF1
/ 2
N-1
≈ 5 / 3 x 1.215 V / 2
15
= 62 µV
(7) The LSB size of the external thermistor voltage measurement when reported in 32-bit format is given by 1 LSB = 5 / 3 x V
REG18
/ 2
N-1
≈
5 / 3 x 1.8 V / 2
23
= 358 nV
(8) The 16-bit LSB size of the divider voltage measurement is given by 1 LSB = 425 / 3 x V
REF1
/ 2
N-1
≈ 425 / 3 x 1.215 / 2
23
= 5.25 mV
(9) Average effective differential input resistance with device operating in NORMAL mode, cell balancing disabled, three or more
thermistors in use, and a 5 V differential voltage applied.
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BQ769142
SLUSE91A – SEPTEMBER 2020 – REVISED FEBRUARY 2021
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