SNAU133
Page 23
If the internal/external clock selection is changed, then the ADC should be re-calibrated.
The required clock amplitude to the ADC may be found in the datasheet as V
IN_CLK
. For the ADC0XD1520, this
range is {0.4Vpp, 2.0Vpp}. However, there is a significant insertion for the Teledyne relay, RF303, and other
components on the ADC0XD1520RB, as shown in Figure 15. To compensate for this insertion loss, use the
recommended values in Table 1. The magnitude shown is for the signal at J11, the External Clock Input SMA, in
order to maintain the proper level at the ADC’s CLK+/- inputs. For example, measure and adjust the amplitude of
the external signal gen filter on a power meter or spectrum analyzer before connecting to the External Clock
Input.
Figure 15. External / internal clock selection circuit on ADC0XD1520RB
Ext Clk Freq
To maintain 0.4Vpp
To maintain 2.0Vpp
1.0 GHz
-2 dBm
+9 dBm
1.2 GHz
+1 dBm
+11 dBm
1.4 GHz
+1 dBm
+12 dBm
1.6 GHz
+3 dBm
+16 dBm
1.8 GHz
+2 dBm
+14.5 dBm
2.0 GHz
+3 dBm
+16 dBm (hit max gen @ 1.8V)
Table 1. External clock frequency relay insertion loss compensation
