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SNAU133

Phase Adjust

: This tab controls the Aperture Delay function.

Figure 13: t

AD

Adjust Panel

•

POL

– Polarity Select – When this bit is selected, the polarity of the ADC sampling clock is

inverted

•

Coarse Phase Adjust

– Sets the approximate amount of coarse Aperture Delay applied.

•

IPA

– Intermediate Phase Adjust – Each code value in this field delays the sample clock by

approximately 11 ps. A value of 000b in this field causes zero adjustment. Maximum combined
adjustment using Coarse Phase Adjust and Intermediate Phase adjust is approximately 2.1 ns.

•

Fine Phase Adjust

– Sets the approximate amount of fine Aperture Delay applied.

Note

: No changes will appear until the

Write Adjust Reg

button is clicked.

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Содержание ADC0XD1520RB

Страница 1: ...SNAU133 Page 1 ADC0XD1520RB Reference Board Users Guide ...

Страница 2: ...Software 2 2 Installing the ADC0XD1520RB Hardware 2 3 Launching the WaveVision 5 Software 2 4 WaveVision 5 User Interface Overview 2 5 System Device Configuration 2 6 Data Capturing 3 0 Secondary Panel Description 4 0 Reference Board Functional Description 4 1 System Block Diagram 4 2 System Description 5 0 Electrical Specification ...

Страница 3: ...ing rate of 3 0 GHz The board showcases the following Texas Instruments devices ADC0XD1520 analog to digital converter LMX2541 clock synthesizer LP3878 and LP38513 ADJ linear LDO regulators LM20242 LM25576 and LM26400 switching regulators LM3880 power sequencing controller LM95233 temperature sensor In addition the board also employs the Xilinx XC4VLX25 11FFG668 Virtex 4 FPGA for the critical func...

Страница 4: ...licity and performance of USB 2 0 connection to the PC Functions with TI s latest WaveVision 5 signal path control and analysis software 1 2 Packing List The ADC0XD1520RB kit consists of the following components ADC0XD1520RB Reference Board Documentation on CD Including o ADC0XD1520RB Users Guide this document o Wavevision 5 Software o ADC0XD1520RB schematic layout o ADC0XD1520RB bill of materials...

Страница 5: ...e 1 ADC0XD1520RB Board Layout Power Switch I ch Sig Q ch Sig Ext Clock Ext Trigger DCLK_RST LMX2541 Int Clock FPGA Xilinx LEDs ADC08D1520 USB Controller USB ADC Control Jumpers Power section Power 12V Auxiliary Data Port FMC connector on bottom ...

Страница 6: ... one shown in Figure 2 as possible This setup along with the board and software configuration described below is what was used to test the reference board at TI s lab This set of conditions produces the stated reference performance which is normally included with each board shipped to customers The objective is to assure that the user can achieve the same performance as that recorded at TI s lab p...

Страница 7: ...0RB Reference Board s I channel input connectors Set the signal generator at one of the frequencies and signal levels stated in the reference performance report Always use high quality RF SMA cables for optimum performance Do not overdrive the signal and clock inputs as the ADC may be damaged Refer to the Electrical Specification section of the datasheet for the voltage tolerance of these inputs I...

Страница 8: ...ystem is ready for an acquisition Where green is on black is off DCLK_LOCKED OVER RANGE_Q CH TRIGGER_ARMED ADC_POWER ADC_CALIBRATION OVER RANGE_I CH FPGA_OPERATIONAL ECM_ENABLED RCOUT1 2_ENABLED NOTE The status LEDs are valid only if the FPGA_OPERATIONAL LED is lit Meaning of the status LED s DCLK_LOCKED If FPGA detects DCLKI and DCLKQ toggling this LED lights TRIGGER_ARMED Lights when H W Trigger...

Страница 9: ...control of features The tabs available on the left side access panels that are pertinent to the current plot window such as channel selection grid selection FFT Readouts and FFT controls The right side panels allow the user to take control of the hardware These include the Signal Source Signal Control and Registers panels the most relevant for this board In addition a small FFT parameter summary b...

Страница 10: ...ntrol jumper area The board should be sent with this jumper in place This means that the ADC will be controlled through the SPI interface and not with jumpers driving the control pins This allows the user to control the ADC s behavior through the WaveVision 5 Registers panel Figure 4 WaveVision 5 overview of control buttons Figure 5 WaveVision 5 main window command buttons ...

Страница 11: ...stogram plot Hardware histograms are available only in conjunction with evaluation boards which can gather histogram data internally This button is enabled only when an evaluation board which supports hardware histograms is attached 5 Acquire Data Click this button to acquire data to the active plot If you have created more than one plot the Active plot has a highlighted title bar 6 Continuous Acq...

Страница 12: ...w 2 Save Plot Displays the Plot Save dialog this button is only active when the plot contains one or more channels with data 3 Reset Zoom Reset X and Y axis zoom to 100 4 Clear Clear data from all channels 5 Print Print the plot 6 Time Domain Display the plot as time domain data 7 FFT Display the plot as an FFT 8 Histogram Display a histogram of the data 9 Close Close this plot ...

Страница 13: ...channel mode capturing and viewing both the I and Q channel data DESI Mode Double Edge Sample interleaved mode with I input DESQ Mode Double Edge Sample interleaved mode with Q input Double Edge Sampling DES Double edge sampling works much in the same way as single edge sampling except that the signals is sampled both on the rising and falling edge of the sample clock This effectively doubles the ...

Страница 14: ...y to select the Channels tab and deselect the Automatically hide inactive channels option box in order to allow both channels to appear on the plot Alternatively one channel may be displayed per plot Figure 7b I and Q mode both channels displayed on one plot ...

Страница 15: ... correct subsequent data captures and display will not be correct Resolution This will always be set to the ADC0XD1520 resolution which is 8 bits Acquisition Size This setting displays and selects the number of samples captured in each acquisition 4K samples is the default with settings up to 32K samples A larger sample size increases the equivalent FFT bandwidth resolution but at the expense of m...

Страница 16: ...s The following is a short description of each tab under the Register panel Settings This tab gives choice of either External Clock or Internal Clock and buttons to initiate FPGA Reset Reset Registers and Calibrate ADC Calibration of the ADC should be performed if changes occur such as device temperature mode changes single channel to dual channel single edge sampling Non DES to double edge sampli...

Страница 17: ... bus clocking follows the SDR mode whereby each data word is output with either the rising or falling edge of DCLK as determined by the OutEdge bit OV Output Voltage This bit determines the LVDS outputs voltage amplitude and has the same function as the OutV pin that is used in the Non extended Control Mode When this bit is set to 1b the normal output amplitude is used When this bit is set to 0b t...

Страница 18: ...the SDR DDR and the Non demux Modes DES and Non DES RTD Resistor Trim Disable When this bit is set to 1b the input termination resistor is not trimmed during the calibration cycle and the DCLK output remains enabled Note that the ADC is calibrated regardless of this setting DLF DES Low Frequency When this bit is set to 1b the dynamic performance of the device is improved when the input clock is le...

Страница 19: ...use pointer or using left right arrow keys once the slider has been selected Although the offset is entered in an 8 bit 0 to 255 relative form it is also displayed in approximate mV I Channel Full Scale The approximate I Channel input full scale range mV peak to peak is selected ranging from a minimum of 560mV to a maximum of 840mV The default setting is 700mV Note No changes will take effect unti...

Страница 20: ...arse Aperture Delay applied IPA Intermediate Phase Adjust Each code value in this field delays the sample clock by approximately 11 ps A value of 000b in this field causes zero adjustment Maximum combined adjustment using Coarse Phase Adjust and Intermediate Phase adjust is approximately 2 1 ns Fine Phase Adjust Sets the approximate amount of fine Aperture Delay applied Note No changes will appear...

Страница 21: ...local board temperature of the LM95233 IC ADC Temperature Provides the approximate die temperature of the ADC0XD1520 FPGA Temperature Provides the approximate die temperature of the Xilinx Virtex 4 FPGA Note No changes will appear until the Update Temperatures button is clicked ...

Страница 22: ...on 5 controls Type Ctrl r to obtain the summary of the acquisition Place the software in continuous mode Item 6 of Figure 6 and then acquire again At this point dynamic performance metrics similar to those shown on the reference data shipped with the board may be obtained One of the basic variables that you may experiment with at this point is to change the input signal magnitude and frequency Ple...

Страница 23: ...le 1 The magnitude shown is for the signal at J11 the External Clock Input SMA in order to maintain the proper level at the ADC s CLK inputs For example measure and adjust the amplitude of the external signal generator filter on a power meter or spectrum analyzer before connecting to the External Clock Input Figure 15 External internal clock selection circuit on ADC0XD1520RB Ext Clk Freq To mainta...

Страница 24: ... Clock DCLK_RST VinI VinQ Analog_3 3V Digital_3 3V Analog_1 9V 12V EEPROM Local Clock 96 MHz DCLKI Q SPI 1 8V USI 1 Conx x2 for external devices Vcmo Analog Front End Boards Plug in Here LMH6518 Balun RF Digital_2 5V Digital_1 8V Digital_1 2V 3 3V 5V GND Analog_3 3 5 0V for off board use Vreg 5V 3 3V Power Sequencing Control Temp Sensor LM95233 I2C ADR DATA FIFO I F uWire SPI 3 3V SE2DIFF Trigger ...

Страница 25: ...ation pin 9 on J15 is removed for DC operation 2 8 2 LMX2541 Clock Synthesis chip The LMX2541xxxx family provides a single chip very low jitter clock solution at frequencies up to 4 0 GHz In this application the LMX2541SQ3030E is used which can be programmed to operate over a range of 2810 3230MHz This output frequency from the VCO is divided to achieve the desired clocking frequency of the ADC On...

Страница 26: ... Vth then a data capture will occur Vth is approximately 2 1V so it is recommended that high trigger voltage is in the range of 2 5V 3 3V The low trigger voltage should be 0V Note that this may be a single shot data capture or a continuous trigger If the trigger is armed but Vtrigger is not greater than Vth within approximately 3 minutes then the software will time out and show the error message B...

Страница 27: ...RB Carrier FMC_PG_M2C J156 Override power good M2C indicates power good from Mez to Carrier J155 Override power good C2M FPGA will output data on FMC FMC_PG_C2M Figure 18 Explanation of Power Good override jumpers for FMC port ADC0xD1520RB ...

Страница 28: ...C0XD1520RB showing FMC port 2 8 4 LM95233 Temperature Sensor Using the TI LM95233 temp sensor chip the ambient ADC0XD1520 and Xilinx FPGA temperatures can be monitored The temperature readings are available through the WV 5 software ...

Страница 29: ...dBm The maximum level at the signal generator is dependent upon the insertion loss from other hardware before the ADC inputs Care should be taken not to exceed the Operating Ratings at the ADC input Clock Input Signal Maximum Operating Voltage 2 0V Recommended generator setting 1 dBm The maximum level at the signal generator is dependent upon the insertion loss from other hardware before the clock...

Страница 30: ...vices described herein Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2012 Texas Instruments Incorporated REGULATORY COMPLIANCE INFORMATION As noted in the EVM User s Guide and or EVM itself this EVM and or accompanying hardware may or may not be subject to the Federal Communications Commission FCC and Industry Canada IC rules For EVMs not subject to the abov...

Страница 31: ...ergy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correc...

Страница 32: ...nnée équivalente p i r e ne dépasse pas l intensité nécessaire à l établissement d une communication satisfaisante Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d antenne énumérés dans le manuel d usage et ayant un gain admissible maximal et l impédance requise pour chaque type d antenne Les types d antenne non inclus dans cette liste ou dont le gain...

Страница 33: ...すのでご注意ください１電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく２実験局の免許を取得後ご使用いただく３技術基準適合証明を取得後ご使用いただくなお本製品は上記のご使用にあたっての注意を譲渡先移転先に通知しない限り譲渡移転できないものとします上記を遵守頂けない場合は電波法の罰則が適用される可能性があることをご留意ください日本テキサスインスツルメンツ株式会社東京都新宿区西新宿６丁目２４番１号西新宿三井ビル http www tij co jp ...

Страница 34: ...tput voltage current power and environmental ranges may cause property damage personal injury or death If there are questions concerning these ratings please contact a TI field representative prior to connecting interface electronics including input power and intended loads Any loads applied outside of the specified output range may result in unintended and or inaccurate operation and or possible ...

Страница 35: ...siness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necess...

Страница 36: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments ADC07D1520RB NOPB ...

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