Texas Instruments ADC DJ 00RF Series, Руководство пользователя

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7.2.3 External Reference Clocking Option
The Reference clock(J17) is provided by an external source. The LMK00304 make two copies of the reference
signal and sends the one copy to LMX2594 to generate the sampling clock for the ADC and LMK04828 uses
the second copy in clock distribution mode to provides the FPGA reference clock, FPGA SYSREF signal. The
ADC SYSREF signal is generated by the LMX2594.
Figure 7-3 shows the block diagram of external reference
clocking option:
The EVM can be configured to use external reference clocking option with the following steps (see Figure 7-5 ):
• Remove C2 and C3, populate R171 and R174
• Remove C60 and C61, populate C52 and C306
• Install Jumper J13
SYNC
SYSREFREQ
OSCIN RFOUTA
RFOUTB
SDCLKx
SDCLKx
DCLKx
SDCLKx
DA[15:0]
SYNC
FPGA_CLK[3:0]
FPGA_SYSREF
CLKIN0
CLKIN1
LMK61E2
LMK00304
SDCLKx
LMK04828
LMX2594
ADC12DJ5200RF
CLK
SYSREF
DA[15:0]
FMC
SYNC
REFCLK
(J17)
260 MHz
SYSREF
32.5 MHz
Board SYNC
External
Referencel Clock
/N
SYSR
EF
3
2
.5
MH
z
Figure 7-3. External Reference Clocking System Block Diagram
HSDC Pro Settings for Optional ADC Device Configuration www.ti.com
20 ADCxxDJxx00RF Evaluation Module SLAU640A – APRIL 2019 – REVISED JUNE 2021
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