3.2.4.5 Counter Status Register CNTSTAT (Offset 0x0130)
Bit
Symbol
Description
Access
Reset
Value
31:10
-
Reserved
Read: always reads as '0'
R
0
9
CIRQ
Pending Control Mode Interrupts (Read),
Interrupt acknowledge (Write)
On a read-access this bit shows a pending Control Mode Interrupt.
Pending interrupts are marked with a '1'.
An interrupt is acknowledged by writing a '1' to this bit.
R/C
0
8
MIRQ
Pending Match Interrupts (Read),
Interrupt acknowledge (Write)
On a read-access this bit shows a pending Match Interrupt. Pending
interrupts are marked with a '1'.
An interrupt is acknowledged when the MAT bit is cleared.
R
0
7
SGL
Single Cycle active
In Single Cycle counting mode this bit is set to ‘1’ if the counter is
enabled.
R
0
6
OVFL
Counter Data Register Latch Overflow
If a Latch Mode event occurs while the Counter Data Register Latch is
active, this bit will be set to indicate that data was lost. This bit must be
reset by writing a '1' to this bit.
R/C
0
5
CDLT
Counter Data Register Latch
This bit is set to '1', when the Counter Data Register is latched due to a
'Latch on Control. This bit is cleared after a read access to the Output
Register or by writing a '1' to this bit.
R/C
0
4
DIR
Count Direction
This bit indicates the direction, the counter is counting to. '1' indicates
up, '0' indicates down. In the 'Up/Down Count' mode this bit indicates
the direction at the last count. In the 'Direction Count' mode this bit
corresponds to the Y-input.
R
0
3
SGN
Sign
The Sign bit is set to '1' when the counter overflows, and set to '0'
when the counter underflows.
After reset or power-up this bit should be considered as "don't care"
until the first Carry or Borrow occurred.
R
0
2
MAT
Match
This bit is set to '1' when the counter value matches the value of the
Counter Compare Register. This bit must be reset by writing a '1' to
this bit.
R/C
0
1
CRY
Carry
This bit is set to '1' when the counter changes from 0xFFFFFFFF to
0x00000000. This bit must be reset by writing a '1' to this bit.
R/C
0
0
BOR
Borrow
This bit is set to '1' when the counter changes from 0x00000000 to
0xFFFFFFFF. This bit must be reset by writing a '1' to this bit.
R/C
0
Table 3-30: Counter Status Register
TPMC851 User Manual Issue 1.0.9
Page 36 of 65
