Tews Technologies TPMC851 Скачать руководство пользователя страница 60 | Manualshive

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Input Mode

Count Mode

Control Mode

Additional Configuration

Timer Mode Down

Single Cycle

Load Mode

Set CNTPRL to watchdog time,
CNTCMP to zero, enable
counter match IRQ

6.5.4.2 Event Counting

In this configuration, input pulses or events occurring at the input pin of the counter are counted up to a
programmed count limit. Upon reaching the count limit, the counter output will generate an interrupt. To arm the
counter for the next measurement, reset the counter in the Counter Command Register.

Input Mode

Count Mode

Control Mode

Additional Configuration

U/D Count

Single Cycle

none

Set CNTCMP to limit, enable
counter match IRQ

6.5.4.3 Input Pulse Width Measurement

For pulse-width measurement, the pulse-width being measured serves as a clock gate for an up-counter. To arm
the  counter  for a  measurement,  reset  the  counter  in the  Counter  Command  Register.  The  measurement starts
with  the  next  rising  edge  and  ends  with  the  falling  edge  of  the  gate  signal.  An  interrupt  is  generated  upon
completion  of  the  pulse-width  measurement.  The  up-counter  uses  the  internal  clock  prescaler  at  the  counter’s
clock pin. Use following formula to calculate the pulse-width:

Pulse Width = Counter Value / Clock Frequency

Input Mode

Count Mode

Control Mode

Additional Configuration

Timer Mode Up

Single Cycle

Gate Mode

Enable control mode IRQ

6.5.4.4 Mechanical System Positioning

If a mechanical system provides position switches, these can be used for various purposes:

Establish a known home

Input Mode

Count Mode

Control Mode

Additional Configuration

U/D Count

Cycle Counter

Reset Mode

Enable control mode IRQ

Establish a known reference position

Input Mode

Count Mode

Control Mode

Additional Configuration

U/D Count

Cycle Counter

Load Mode

Enable control mode IRQ

Capture a position

Input Mode

Count Mode

Control Mode

Additional Configuration

U/D Count

Cycle Counter

Latch Mode

Enable control mode IRQ

Interrupts

6.6

All Interrupts are requested at the LINT1 input of the PCI9030 Target Chip.

Interrupts are generated only if the Master Interrupt Enable (MIE) is enabled in the Interrupt Control
Register ICR.

6.6.1 Interrupt Sources

IRQ

IRQ Description

Enable IRQ

Acknowledge IRQ

TPMC851 User Manual Issue 1.0.9

Page 60 of 65

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Содержание TPMC851

Страница 1: ...tifunction I O 16 bit ADC DAC TTL I O Counter Version 1 0 User Manual Issue 1 0 9 September 2014 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 4058 0 Fax 49 0 4101 4058...

Страница 2: ...ime without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with...

Страница 3: ...tion Clarified Sequencer Start Stop Control in ADCSEQCONT September 2006 1 5 Added note to ADC Control Register October 2006 1 0 6 New notation for HW Engineering Documentation Releases March 2009 1 0...

Страница 4: ...3 1 Line Direction Register LINEDIR Offset 0x0100 27 3 2 3 2 Line Debounce Enable Register LINEDEB Offset 0x0104 28 3 2 3 3 Line Debounce Time Register LINEDBT Offset 0x0108 28 3 2 3 4 Line Input Regi...

Страница 5: ...6 5 1 Input Modes 57 6 5 1 1 Timer Mode 57 6 5 1 2 Direction Count 57 6 5 1 3 Up Down Count 57 6 5 1 4 Quadrature Count 58 6 5 2 Count Modes 58 6 5 2 1 Divide by N 58 6 5 2 2 Single Cycle 58 6 5 3 Co...

Страница 6: ...GISTER 17 TABLE 3 8 ADC SEQUENCER CONTROL REGISTER 19 TABLE 3 9 ADC SEQUENCER STATUS REGISTER 20 TABLE 3 10 ERROR FLAG IRQ GENERATION 20 TABLE 3 11 ADC SEQUENCER TIMER REGISTER 21 TABLE 3 12 ADC SEQUE...

Страница 7: ...ABLE 4 2 PCI9030 PCI BASE ADDRESS USAGE 42 TABLE 4 3 PCI9030 LOCAL CONFIGURATION REGISTER 43 TABLE 4 4 CONFIGURATION EEPROM TPMC851 10R 44 TABLE 5 1 LOCAL BUS LITTLE BIG ENDIAN 45 TABLE 6 1 SEQUENCER...

Страница 8: ...ernal event Conversion data is stored in a data RAM The 8 analog output channels are realized by eight 16 bit digital to analog converters DACs The conversion time is 10 s An operational amplifier dri...

Страница 9: ...aler o Up Down count first counter input counts up second input counts down o Direction count first counter input counts second input sets count direction o Quadrature count with 1x 2x or 4x resolutio...

Страница 10: ...70Vpp Calibration Data Calibration data for gain and offset correction in ID PROM Resolution 16 bit with no missing codes Conversion Time 1 25 s without channel gain change 17 25 s with channel gain...

Страница 11: ...2V DC Temperature Range Operating Storage 40 C to 85 C 40 C to 85 C MTBF 330000 h MTBF values shown are based on calculation according to MIL HDBK 217F and MIL HDBK 217F Notice 2 Environment GB 20 C T...

Страница 12: ...s The registers shorter than 32 bit are filled with zeros on long word read accesses Refer to chapter Big Little Endian or the following table for correct word or byte wide accesses Access Width Regis...

Страница 13: ...x0110 LINEOUT Line Output Register 0x0114 LINEIEN Line Interrupt Enable Register 0x0118 LINEIST Line Interrupt Status Register 0x011C Not used 0x0120 CNTPRL Counter Preload Register 0x0124 CNTCMP Coun...

Страница 14: ...disabled 1 IRQ after Settling Time enabled An interrupt will be generated after the settling time has elapsed SETTL_BUSY changes from 1 to 0 For pending interrupts and interrupt acknowledge see the AD...

Страница 15: ...d gain Subsequent write accesses are ignored until the settling time has elapsed This register is developed for a word 16 bit or long word 32 bit read write access Byte accesses on this register are n...

Страница 16: ...ent Full Scale Range 10V 5V 2 5 1 25 Least Significant Bit 305 2 V 152 6 V 76 2 V 38 15 V FSR 1LSB 9 999695V 4 999847V 2 499924V 1 249962V 0x7FFF Midscale 1LSB 305 2 V 152 6 V 76 2 V 38 15 V 0x0001 Mi...

Страница 17: ...ates that the required settling time after a write to the CONTREG register is not yet done This bit is set by writing to the CONTREG register The bit is cleared when the required settling time has ela...

Страница 18: ...he conversion is started The ADC_BUSY bit in the ADC Status Register indicates if the conversion data in the ADC Data Register is valid ADC_BUSY bit 0 It is allowed to set up a new channel gain by wri...

Страница 19: ...Mode Sequencer stops immediately No DATA AV will be issued 1 Starts the Sequencer immediately R W 0 Table 3 8 ADC Sequencer Control Register If an error flag DATA_OVERFLOW_ERROR TIMER_ERROR I RAM_ERRO...

Страница 20: ...Flag always reads as 0 R C 0 1 DATA OVERFLOW ERROR Data Overflow Error Flag Set by the sequencer if the last sequencer instruction is done and the Data Available Flag of the previous sequence has not...

Страница 21: ...the instruction RAM Assure that the time needed to complete a sequence is suitable to the chosen sequence timer value If the sequence timer elapses while a sequence is still in progress a timer error...

Страница 22: ...hannel is configured as differential channel the instruction of the associated channel is ignored see following chart or chapter Pin Assignment I O Connector for the associated channels Within a seque...

Страница 23: ...x60 Channel 17 N A Input for Channel 1 0x64 Channel 18 N A Input for Channel 2 0x68 Channel 19 N A Input for Channel 3 0x6C Channel 20 N A Input for Channel 4 0x70 Channel 21 N A Input for Channel 5 0...

Страница 24: ...trigger Dig I O Line 1 In the Simultaneous Update modes it is required to load the DACs with data via the DAC Data Registers This data is buffered until the trigger event on which all DACs are update...

Страница 25: ...flow condition for the sequencer data RAM 1 Sequencer Data Underflow sequencer is ready for the next sequence but the user has not yet confirmed new data in sequencer data RAM 0 All DAC Data Registers...

Страница 26: ...e for the sequencer timer is derived from an on board 40 MHz oscillator 3 2 2 4DAC Data Register DACDATA 1 8 Offset 0x00D0 Offset 0x00EC Bit Symbol Description Access Reset Value 31 16 Reserved Write...

Страница 27: ...NEDIR0 operation R W 0 15 LINEDIR15 I O Line 15 0 TTL I O line as Input 1 TTL I O line as Output R W 0 14 LINEDIR14 I O Line 14 0 13 LINEDIR13 I O Line 13 0 12 LINEDIR12 I O Line 12 0 11 LINEDIR11 I O...

Страница 28: ...ble Register For the enabled I O lines a digital debounce filter will be applied The debounce duration can be programmed in the Line Debounce Time Register LINEDBT The digital input signal must have d...

Страница 29: ...readback functionality 0 TTL I O line logic low 1 TTL I O line logic high R 0 14 LINEIN14 I O Line 14 0 13 LINEIN13 I O Line 13 0 12 LINEIN12 I O Line 12 0 11 LINEIN11 I O Line 11 0 10 LINEIN10 I O L...

Страница 30: ...TTL I O line logic low 1 TTL I O line logic high R W 0 14 LINEOUT14 I O Line 14 0 13 LINEOUT13 I O Line 13 0 12 LINEOUT12 I O Line 12 0 11 LINEOUT11 I O Line 11 0 10 LINEOUT10 I O Line 10 0 9 LINEOUT9...

Страница 31: ...0 17 LINEIENN1 I O Line 1 0 16 LINEIENN0 I O Line 0 0 15 LINEIENP15 I O Line 15 0 Disable interrupt for positive transitions for I O line 1 Enable interrupt for positive transitions for I O line An i...

Страница 32: ...ine 4 0 19 LINEISTN3 I O Line 3 0 18 LINEISTN2 I O Line 2 0 17 LINEISTN1 I O Line 1 0 16 LINEISTN0 I O Line 0 0 15 LINEISTP15 I O Line 15 Interrupt status for positive transitions Read access 0 no int...

Страница 33: ...nterrupt is generated R W 1 Table 3 27 Counter Compare Register 3 2 4 3Counter Data Register CNTDATA Offset 0x0128 Bit Symbol Description Access Reset Value 31 0 CNTDATA Counter Data Register This Reg...

Страница 34: ...Enable Match Interrupt 0 Match Interrupt disabled 1 Match Interrupt enabled An interrupt will be generated when the counter value matches the Counter Compare Register CNTCMP For pending interrupts an...

Страница 35: ...Mode Up Internal Clock Prescaler 010 Timer Mode Down Internal Clock Prescaler 011 Direction Count I O line 2 3 100 Up Down Count I O line 2 3 101 Quadrature Count 1x I O line 2 3 110 Quadrature Count...

Страница 36: ...et to 1 when the Counter Data Register is latched due to a Latch on Control This bit is cleared after a read access to the Output Register or by writing a 1 to this bit R C 0 4 DIR Count Direction Thi...

Страница 37: ...Counter Write 1 to load the counter with the value of the Counter Preload Register CNTPRL This bit is cleared immediately after a write access W 0 0 RCNT Reset Counter Write 1 to reset the counter Th...

Страница 38: ...gister DACSEQSTAT R 0 3 SEQ IRQ Pending ADC Sequencer Interrupt This interrupt must be acknowledged in the ADC Sequencer Status Register ADCSEQSTAT R 0 2 IRQST Pending IRQ after Settling Time This int...

Страница 39: ...PCI Configuration Space The calibration data values are determined at factory and stored in this ROM space There is one Offset Error value and one Gain Error value for each ADC gain which are valid f...

Страница 40: ...OffsetERROR 16 0x22 DAC Channel 5 GainERROR 16 0x24 DAC Channel 6 OffsetERROR 16 0x26 DAC Channel 6 GainERROR 16 0x28 DAC Channel 7 OffsetERROR 16 0x2A DAC Channel 7 GainERROR 16 0x2C DAC Channel 8 O...

Страница 41: ...C PCI Base Address 3 for Local Address Space 1 Y FFFFFFC0 0x20 PCI Base Address 4 for Local Address Space 2 Y FFFFFFC0 0x24 PCI Base Address 5 for Local Address Space 3 Y 00000000 0x28 PCI CardBus Inf...

Страница 42: ...ired PCI Expansion ROM size For example if bit 5 of a PCI Base Address Register is detected as the first bit set to 1 the PCI9030 is requesting a 32 byte space address bits 4 0 are not part of base ad...

Страница 43: ...p Register Space 2 0x0000_0301 Enabled Base Address 0x0300 0x20 Local Re map Register Space 3 0x0000_0000 Not used 0x24 Local Re map Register ROM 0x0000_0000 Not used 0x28 Local Address Space 0 Descri...

Страница 44: ...0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x90 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xA0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xB0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x...

Страница 45: ...Big Endian Little Endian 32 Bit 32 Bit Byte 0 D 31 24 Byte 0 D 7 0 Byte 1 D 23 16 Byte 1 D 15 8 Byte 2 D 15 8 Byte 2 D 23 16 Byte 3 D 7 0 Byte 3 D 31 24 16 Bit upper lane 16 Bit Byte 0 D 31 24 Byte 0...

Страница 46: ...indicates Big Endian and a value of 0 indicates Little Endian Use the PCI Base Address 0 Offset or PCI Base Address 1 Offset Short cut Offset Name LAS0BRD 0x28 Local Address Space 0 Bus Region Descrip...

Страница 47: ...rrected by multiplying the data value with a correction factor The data correction values are obtained during factory calibration and are stored in the Calibration Data ROM 6 1 1 ADC Correction Formul...

Страница 48: ...most everything is automated and the converter operation is transparent to the user Use this mode to convert all channels at specific time intervals or to always have current data available 6 2 1 Manu...

Страница 49: ...s are updated Channels not enabled in the Sequencer Instruction RAM are not updated and may contain invalid data from former conversions After that the DATA_AV flag must be cleared by writing a 1 to t...

Страница 50: ...quencer Time is shorter than the sequence itself not in Sequencer Continuous Mode Sequencer stops after the last instruction is done Timer Error Flag is set If enabled an interrupt request will be ass...

Страница 51: ...is issued which signals that the conversion data is available in the ADCDATA Register Acknowledge the Interrupt in the ADC Status Register ADCSTAT ADC_READY 1 and read ADCDATA Figure 6 1 Flow Fastest...

Страница 52: ...C Conversion Start Register ADCCONV to start the next conversion of this channel acknowledge the Interrupt in the ADC Status Register ADCSTAT ADC_IRQ 1 and read ADCDATA Figure 6 2 Flow Fastest convers...

Страница 53: ...nd start the Sequencer in the Sequencer Control Register ADCSEQCONT After completion of the sequence a Sequencer Interrupt is issued which signals that the conversion data is available in the Sequence...

Страница 54: ...ese channels in the Sequencer Instruction RAM Set the Sequencer Timer Register ADCSEQTIMER to 0x0000 Start the Sequencer in the Sequencer Control Register ADCSEQCONT Read the data from the Sequencer D...

Страница 55: ...ta Registers don t immediately update the DACs Instead this data is buffered until a trigger event This trigger event simultaneously updates all DACs with the buffered data The Simultaneous Update Mod...

Страница 56: ...e trigger signal for the DAC sequencer is available for external use on Dig I O Line 1 In this case the settings in the Line Direction Register for these I O lines LINEDIR0 resp LINEDIR1 are overridde...

Страница 57: ...ode the counter uses an internal clock prescaler as input Bits Prescaler Clock frequency 00 1x 40 MHz 01 2x 20 MHz 10 4x 10 MHz 11 8x 5 MHz Table 6 4 Clock Prescaler 6 5 1 2Direction Count The counter...

Страница 58: ...un until disabled The counter is loaded with the content of the preload register every time the counter creates a borrow or a carry This mode assumes that the counter counts to one direction only 6 5...

Страница 59: ...the Counter Data Register It will remain latched until the Counter Data Register is read or the latch is released with the CDLT bit in the Counter Status Register 6 5 3 4Gate Mode The I O Line 4 enabl...

Страница 60: ...ulse width measurement The up counter uses the internal clock prescaler at the counter s clock pin Use following formula to calculate the pulse width Pulse Width Counter Value Clock Frequency Input Mo...

Страница 61: ...Register DACCONT DAC Sequencer Status Register DACSEQSTAT LINEIST Digital I O line IRQ Line Interrupt Enable Register LINEIEN Line Interrupt Status Register LINEIST CIRQ Counter control mode interrupt...

Страница 62: ...ect connection of a wide range of sensors and instrumentation The maximum analog input voltage range is 10V at a gain of 1 Figure 7 1 ADC Input Wiring Make sure that all unused analog input pins are t...

Страница 63: ...i state output function and an electronic protection array for ESD and overvoltage protection See the following figure for more information of electrical circuitry Figure 7 3 TTL I O Interface While p...

Страница 64: ...ADC Diff 11 13 ADC SE 12 ADC Diff 12 47 ADC SE 28 ADC Diff 12 14 ADC SE 13 ADC Diff 13 48 ADC SE 29 ADC Diff 13 15 ADC SE 14 ADC Diff 14 49 ADC SE 30 ADC Diff 14 16 ADC SE 15 ADC Diff 15 50 ADC SE 31...

Страница 65: ...f the sequencer is to be used these two dummy conversions are absolutely necessary If one of TEWS TECHNOLOGIES software drivers is used these two dummy conversions are already included Open Multiplexe...

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