DE10-Standard
User Manual
109
www.terasic.com
January 19, 2017
All the Avalon Conduit signals of these peripherals are connected to the I/O pins of the SoCFPGA
on DE10-Standard board as shown in the
Figure 7-3
.
Figure 7-3 Connection in the top design
7
7
.
.
5
5
C
C
o
o
m
m
p
p
i
i
l
l
e
e
a
a
n
n
d
d
P
P
r
r
o
o
g
g
r
r
a
a
m
m
m
m
i
i
n
n
g
g
In the Qsys tool, click the menu item “Generate
Generate…” to generate source code for the
system and then close the Qsys tool. Now, users can start the compile process by clicking the menu
item “Processing
Start Compilation”.
Because .tcl files of SDRAM DDR3 controller for HPS had been executed in GHRD project,
developers can skip this procedure. If developers’ Quartus project is not developed based on the
GHRD project, please remember to execute the .tcl files of SDRAM DDR3 controller, as show in
Figure 7-4
, before executing ‘Start Compilation’.
The TCL Scripts dialog can be launched by clicking the menu item “Tools
TCL Scripts…”.
<qsys_system_name>
_parameters.tcl
and <qsys_system_name>
_pin_assignments.tcl
tcl files
should be executed, where <qsys_system_name> is the name of your Qsys system. Run this script
to assign constrains tor the SDRAM DDR3 component.
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