Terasic Apollo Carrier Board, Руководство пользователя

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Apollo Carrier Board
User Manual 7 www.terasic.com
September 22, 2020
Table 2-1 General User I/O Pin Assignments, Schematic Signal Names, and Functions
Schematic
Signal Name
Description I/O Standard
FMC
Pin Num.
Apollo S10
FPGA Pin Num.
LED[0]
Driving logic 0 on the I/O port turns
the LED ON. Driving logic 1 on the
I/O port turns the LED OFF.
1.8 V D17 PIN_E21
LED[1] 1.8 V D18 PIN_D21
LED[2] 1.8 V H19 PIN_G19
LED[3] 1.8 V H20 PIN_F19
SW[0]
High logic level when SW in the
UPPER position.
1.8 V D14 PIN_G20
SW[1] 1.8 V D15 PIN_H20
KEY[0] High Logic Level when the button is
not pressed
1.8 V C14 PIN_J21
KEY[1] 1.8 V C15 PIN_H21

2x20 GPIO Header (Timing Expansion Header)
The board has one 2x20 GPIO headers. The header has 36 user pins connected to the FMC
connector via voltage level translator (See Figure 2-4 ). The 2x20 GPIO I/ o standard can support
three I / O standards including 1.8, 2.5 and 3.3V. Users can select the desired voltage setting
through the JP2 header (See Figure 2-5 and Table 2-2 ). It also comes with DC +5V (VCC5), DC
+3.3V (VCC3P3), and two GND pins. Figure 2-6 and Figure 2-7 show the I/O distribution of the
GPIO connector. The maximum power consumption allowed for a daughter card connected to the
GPIO ports is shown in Table 2-3 and Table 2-4 shows all the pin assignments of the GPIO
connector. The pin-out of JP1 is shown in
Figure 2-4 Connection between 2x20 GPIO and Apollo S10 SoM