Appendix A: Specifications
AĆ14
MTX100 MPEG Recorder & Player User Manual
188 bytes
DATA 0-7
DCLK
PSYNC
DVALID
DATA 0-7
DCLK*
DATA 0-7
DCLK*
Output data delay
Input clock pulse width
Input data hold time
Th
T/2
"
T/10
T (f/1)
5 ns
5 ns
* In the universal parallel/serial and BNC serial interfaces,
the polarity of DCLK can be inverted.
ThĂ=ĂT/2
"
T/10: DVBĆSPI and universal parallel interfaces
ThĂ=ĂT/5
"
T/10: universal serial and BNC serial interfaces
TransitionĂperiod
Figure AĆ1: Timing diagram of the DVBĆSPI, universal parallel/serial, and BNC serial interfaces
Содержание MTX100
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